StarT-NG: Delivering seamless parallel computing

Chiou, Derek; Ang, Boon Seong; Greiner, R.; Arvind, .; Hoe, James C.; Beckerle, Michael J.; Hicks, James E.; Boughton, G. A.

doi:10.1007/bfb0020458

Cited by 28 publications

(15 citation statements)

References 14 publications

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“…To avoid deadlock, the CPU must handle interrupts while memory accesses are outstanding, precluding some existing offthe-shelf microprocessors. FLASH [13], StarT-NG [11], and Typhoon [37] perform all protocol processing-on both the directory and the caching nodes-in software. FLASH and Typhoon execute protocol software on a custom processor integrated with the network interface; FLASH also incorporates the memory controller on this device.…”

Section: Macro-evaluationmentioning

confidence: 99%

Decoupled hardware support for distributed shared memory

Reinhardt

Pfile

Wood

1996

Proceedings of the 23rd Annual International Symposium on Computer Architecture

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This paper investigates hardware support for fine-grain distributed shared memory (DSM) in networks of workstations.To reduce design time and implementation cost relative to dedicated DSM systems, we decouple the functional hardware components of DSM support, allowing greater use of off-the-shelf devices.We present two decoupled systems, Typhoon-O and Typhoon-1. Typhoon-O uses an off-the-shelf protocol processor and network interface; a custom access control device is the only DSM-specific hardware. To demonstrate the feasibility and simplicity of this access control device, we designed and built au FPGA-based version in under one year. Typhoon-1 also uses an off-the-shelf protocol processor, but integrates the network interface and access control devices for higher performance.We compare the performance of the two decoupled systems with two integrated systems via simulation. For six benchmarks on 32 nodes,~phoon-O ranges from 30% to 309% slower than the best integrated system, while Typhoon-1 ranges from 13% to 132% slower. Four of the six benchmarks achieve speedups of 12 to 18 on Typhoon-O and 15 to 26 on Typhoon-1, compared with 19 to 35 on the best integrated system. Two benchmarks are hampered by high communication overheads, but selectively replacing shared-memory operations with message passing provides speedups of at least 16 on both decoupled systems. These speedups indicate that decoupled designs can potentially provide a cost-effective alternative to complex high-end DSM systems.

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Section: Macro-evaluationmentioning

confidence: 99%

Decoupled hardware support for distributed shared memory

Reinhardt

Pfile

Wood

1996

Proceedings of the 23rd Annual International Symposium on Computer Architecture

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“…Several research machines have been designed around this distributed-memory/message-passing paradigm: Alewife [1], AP1000ϩ [8], EM-4 [15,16], EM-X [11], and *T : NG [5,13]. Also, some commercial machines have been or are being built around this scheme: Cray T3E [17], IBM SP-2 [2], Intel ASCI [12], and Tera MTA [3].…”

Section: Introductionmentioning

confidence: 99%

Data and Workload Distribution in a Multithreaded Architecture

Sohn

Sato

Yoo

et al. 1997

Journal of Parallel and Distributed Computing

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“…The cache coherence techniques used in existing commercially available multiprocessors are mainly hardware-based, such as a snoopy cache protocol [2] or a hardware directory-based scheme [3,4] . However, in order to reduce the hardware complexity and/or increase the flexibility, many researchers have considered migrating the coherence protocol, or parts of it, to software [5][6][7][8] . Shared virtual memory (SVM) systems go even further by completely supporting the protocol mechanisms at the operating system or application level using the virtual memory system [9] .…”

Section: Introductionmentioning

confidence: 99%

Computer Simulator: An Educational Tool for Computer Architecture

Hesson¹

2006

American Journal of Applied Sciences

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Abstract:The great advancement in computer architecture and cache memory design and technology had a considerable influence on the way computer architecture was taught in universities. This requires students to be able to visualize the detailed activities that take place within a computer processor and its interaction with memory system. Computer simulators could effectively be used to enhance the understanding and comprehension of cache memory operation. The main objective of this project was to design and implement a computer simulator that was used as an educational tool. This paper presents design specifications, implementation and the functional and structural components of this simulator. This allows students understand the concepts and theory of the computer hardware topics by constructing and verifying knowledge, testing and comparing several different configurations and memory access. Although there was a large number of computer simulators in the market, this simulator differs in the way it contains a specially designed assembler that feeds the simulator with the binary code. In this context it was a tool that provides a high educational value that, on one hand, helps students learn to write an error-free assembly code and on the other hand comprehend the activities that take place during the execution of the program under different settings. At the front-end of the system there are two parts; the editor and the simulator while at the back-end there are the system specially developed assembler and database.

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StarT-NG: Delivering seamless parallel computing

Cited by 28 publications

References 14 publications

Decoupled hardware support for distributed shared memory

Decoupled hardware support for distributed shared memory

Data and Workload Distribution in a Multithreaded Architecture

Computer Simulator: An Educational Tool for Computer Architecture

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