State of the art baseband DSP platforms for Software Defined Radio: A survey

Anjum, Omer; Ahonen, Toni; Garzia, Fabio; Nurmi, Jari; Brunelli, Claudio; Berg, Heikki

doi:10.1186/1687-1499-2011-5

Cited by 27 publications

(14 citation statements)

References 28 publications

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“…A good overview of SDR solutions can be found in Anjum et al [2011]. Recent studies have shown that even multicore architectures can be power efficient in scenarios with tight performance requirements [Horowitz and Dally 2004;Asanovic et al 2006].…”

Section: Introductionmentioning

confidence: 99%

Tomahawk

Arnold

Matúš

Noethen

et al. 2014

ACM Trans. Embed. Comput. Syst.

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Heterogeneity and parallelism in MPSoCs for 4G (and beyond) communications signal processing are inevitable in order to meet stringent power constraints and performance requirements. The question arises on how to cope with the problem of system programmability and runtime management incurred by the statically or even dynamically varying number and type of processing elements. This work addresses this challenge by proposing the concept of a heterogeneous many-core platform called Tomahawk. Apart from the definition of the system architecture, in this approach a unified framework including a model of computation, a programming interface and a dedicated runtime management unit called CoreManager is proposed. The increase of system complexity in terms of application parallelism and number of resources may lead to a dramatic increase of the management costs, hence causing performance degradation. For this reason, the efficient implementation of the CoreManager becomes a major issue in system design. This work compares the performance and capabilities of various CoreManager HW/SW solutions, based on ASIC, RISC and ASIP paradigms. The results demonstrate that the proposed ASIP-based solution approaches the performance of the ASIC realization, while preserving the full flexibility of the software (RISC-based) implementation.

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Section: Introductionmentioning

confidence: 99%

Tomahawk

Arnold

Matúš

Noethen

et al. 2014

ACM Trans. Embed. Comput. Syst.

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“…In order to find a solution for the optimal coefficient vector of the kth ADIR filter, we substitute Equation (16) back into the cost function in Equation (12) and attain the following quadratic form in w k (n):…”

Section: Optimization Problem Statementmentioning

confidence: 99%

“…The concept of software radio on the other hand relies on the development of DSP technology, that is flexible, reconfigurable, and reprogrammable by software to adapt to an environment where there are multiple services, standards, and frequency bands [11]. Correspondingly, the infrastructure in a software radio system is generally required to use reconfigurable VLSI hardware components such as DSP chip sets [12], FPGAs [13], embedded processors [14], and even general purpose processors [15].…”

Section: Introductionmentioning

confidence: 99%

Adaptive reconfigurable V-BLAST type equalizer for cognitive MIMO-OFDM radios

Ozden

2015

EURASIP J. Adv. Signal Process.

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An adaptive channel shortening equalizer design for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) radio receivers is considered in this presentation. The proposed receiver has desirable features for cognitive and software defined radio implementations. It consists of two sections: MIMO decision feedback equalizer (MIMO-DFE) and adaptive multiple Viterbi detection. In MIMO-DFE section, a complete modified Gram-Schmidt orthogonalization of multichannel input data is accomplished using sequential processing multichannel Givens lattice stages, so that a Vertical Bell Laboratories Layered Space Time (V-BLAST) type MIMO-DFE is realized at the front-end section of the channel shortening equalizer. Matrix operations, a major bottleneck for receiver operations, are accordingly avoided, and only scalar operations are used. A highly modular and regular radio receiver architecture that has a suitable structure for digital signal processing (DSP) chip and field programable gate array (FPGA) implementations, which are important for software defined radio realizations, is achieved. The MIMO-DFE section of the proposed receiver can also be reconfigured for spectrum sensing and positioning functions, which are important tasks for cognitive radio applications. In connection with adaptive multiple Viterbi detection section, a systolic array implementation for each channel is performed so that a receiver architecture with high computational concurrency is attained. The total computational complexity is given in terms of equalizer and desired response filter lengths, alphabet size, and number of antennas. The performance of the proposed receiver is presented for two-channel case by means of mean squared error (MSE) and probability of error evaluations, which are conducted for time-invariant and time-variant channel conditions, orthogonal and nonorthogonal transmissions, and two different modulation schemes.

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“…The ADC and DAC are theconnection between the physical world of continuous analog signals and the world of discrete digital samples handled by software.Baseband signal processing operations are defined by programmable designs running on digital hardware.This device is available in various forms on single-chip custom Integrated Circuits (ICs), of which the most commonly used for software radio are Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), General-Purpose Processors (GPPs), Application Specific Integrated Circuits (ASICs), and System-on-Chip (SoC) with hardware accelerators [21], [24], [25].…”

Section: Evolve To Build Cognitive Radiomentioning

confidence: 99%