State-of-the-art in rapid prototyping

Glesner, M.; Kirschbaum, A.

doi:10.1109/sbcci.1998.715411

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…Subsection 3.1 and 3.2 presents only technical features. We will implement both architectures using VHDL (VHSIC Hardware Description Language) [21] and FPGA (Field Programmable Gate Array) [21] in the future.…”

Section: Didactic Architecture Modelsmentioning

confidence: 99%

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Didactic architectures and simulator for network processor learning

Freitas

Martins

2003

Proceedings of the 2003 Workshop on Computer Architecture Education Held in Conjunction With the 30th International Symposium O

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In our university, we are developing a project about Reconfigurable Network Processors (RNP). There are four important results: Reconfigurable CISC Network Processor (RCNP) architecture, Reconfigurable RISC Network Processor (R2NP) architecture, Network Processor Simulator (NPSIM), and a performance analytical model for the ISA (Instruction Set Architecture ). The architectures and the simulator are not commercial products, but conceptual models. This paper shows the main functionality of those four results and the their applicability on the Network Processor learning. As our Network Processor architectures and simulator are simpler than commercial products, their conceptual models can aid students to learn network processors concepts, as a first step to understand other complex architectures.

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Section: Didactic Architecture Modelsmentioning

confidence: 99%

“…Our future works are: To simulate R2NP using Rconf_KMT (Reconfigurable Simulation Tool) [26] and VHDL (VHSIC Hardware Description Language) [21], prototype using FPGA (Field Programmable Gate Array) [21], simulate it in a real network system [2,28], and to develop didactic environment to learn Network Processors.…”

mentioning

confidence: 99%

Didactic architectures and simulator for network processor learning

Freitas

Martins

2003

Proceedings of the 2003 Workshop on Computer Architecture Education Held in Conjunction With the 30th International Symposium O

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“…Simulação do R2NP através de simulador reconfigurável [25] 3. Simulação e prototipação do R2NP em YHDL (VHS/C Hardware Description Language) e FPGA (Field Programmable Gate Array) [ 18] 4. Testes em um sistema de rede real [27] 5.…”

Section: Conclusõesunclassified

R2NP: Processador de Rede RISC Reconfigurável

Freitas

Martins

2002

Anais Do III Workshop Em Sistemas Computacionais De Alto Desempenho (WSCAD 2002)

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Este artigo apresenta o projeto do R2NP (Reconfigurable RISC Network Processor). Sua principal aplicação é como elemento de processamento em sistemas de comunicação de dados, efetivando e estabelecendo conexões e a comunicação entre os equipamentos e dispositivos de rede. As principais características deste processador são a reconfigurabilidade de alguns blocos lógicos, o suporte a multi-protocolo e a topologias dinâmicas, objetivando principalmente a não dependência e a então, flexibilidade de funcionamento. Para isto, o R2NP possui um conjunto de instruções específicas e microarquitetura dedicada para suportar as características mencionadas.

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