Static WCET Analysis of GPUs with Predictable Warp Scheduling

Huangfu, Yijie; Zhang, Wei

doi:10.1109/isorc.2017.24

Cited by 9 publications

(7 citation statements)

References 17 publications

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“…-Device hardware architecture and component-specific (e.g., memory [70,43,68,101,109,104], cache [69,87,154,96,97,194]) -Exclusive access policies [96,97,194] -Software virtualization [84,114,141,41,174,112] -WCET analysis [48,29,30,85,33,16,90,89,88] -Execution time variability reduction and management [18,41,42,67,82,84,88,142,144,200,101,70,68,109,43,141,147,47,81,24] -Temporal diagnostics …”

Section: Temporal Interference and Spatial Interferencementioning

confidence: 99%

GPU Devices for Safety-Critical Systems: A Survey

et al. 2022

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Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance safety-critical systems such as autonomous driving systems. However, the integration of complex, parallel and computationally demanding software functions with different safety-criticality levels on GPU devices with shared hardware resources contributes to several safety certification challenges. This survey categorizes and provides an overview of research contributions that address GPU devices’ random hardware failures, systematic failures and independence of execution.

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Section: Temporal Interference and Spatial Interferencementioning

confidence: 99%

GPU Devices for Safety-Critical Systems: A Survey

et al. 2022

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“…This isolation permits interference-free overlapping of a DRAM/scratchpad transfer from one work-group with a compute phase of another. To schedule work in phases, Sim-D issues instructions from the two active work-groups following a policy similar to greedy-then-round-robin (GTRR) [10]: a work-group continues to occupy the compute resources until a DRAM or scratchpad transfer is issued or an exit is encountered. The resource is then yielded to the work-group in the other slot.…”

Section: Architecturementioning

confidence: 99%

“…outstanding DRAM request handling resources [4], instruction latency [5], kernel-instance and work-group scheduling policies [6], [7] and process context switching latency [8]. These insights have contributed to WCET computation techniques that can be applied in soft real-time systems [9], [10], but sadly have not resulted in a closing timing model suitable for deriving safe WCETs.…”

Section: Introductionmentioning

confidence: 99%

Sim-D: A SIMD Accelerator for Hard Real-Time Systems

Spliet

Mullins

2022

IEEE Trans. Comput.

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Emerging safety-critical systems require high-performance data-parallel architectures and, problematically, ones that can guarantee tight and safe worst-case execution times. Given the complexity of existing architectures like GPUs, it is unlikely that sufficiently accurate models and algorithms for timing analysis will emerge in the foreseeable future. This motivates our work on Sim-D, a clean-slate approach to designing a real-time data-parallel architecture. Sim-D enforces a predictable execution model by isolating compute-and access resources in hardware. The DRAM controller uninterruptedly transfers tiles of data, requested by entire work-groups. This permits work-groups to be executed as a sequence of deterministic access-and compute phases, scheduling phases from up to two work-groups in parallel. Evaluation using a cycle-accurate timing model shows that Sim-D can achieve performance on par with an embedded-grade NVIDIA TK1 GPU under two conditions: applications refrain from using indirect DRAM transfers into large buffers, and Sim-D's scratchpads provide sufficient bandwidth. Sim-D's design facilitates derivation of safe WCET bounds that are tight within 12.7% on average, at an additional average performance penalty of ∼9.2% caused by scheduling restrictions on phases.

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“…The research on static WCET analyses for GPUs has been recently very active. While the well-defined parallel model and the simple kernel software make attractive the use of traditional WCET analysis [42], recent studies showed how GPUs hide many details that can negatively affect the execution time [2] and that it is necessary to develop dedicated WCET analyses [28]. In the opposite view, other works noticed a substantial improvement in the real-time capability of the heterogeneous solution [69] [67].…”

Section: Heterogeneous Hardware and Predictabilitymentioning

confidence: 99%

Timing Predictability in High-Performance Computing With Probabilistic Real-Time

2020

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Application requirements in High-Performance Computing (HPC) are becoming increasingly exacting, and the demand for computational resources is rising. In parallel, new application domains are emerging, as well as additional requirements, such as meeting real-time constraints. This requirement, typical of embedded systems, is difficult to guarantee when dealing with HPC infrastructures, due to the intrinsic complexity of the system. Traditional embedded systems static analyses to estimate the Worst-Case Execution Time (WCET) are not applicable to HPC, because modeling and analyzing all the system's hardware and software components is not practical. Measurement-based probabilistic analyses for the WCET emerged in the last decade to overcome these issues, but it requires the system to satisfy certain conditions to estimate a correct and safe WCET. In this work, we show the emerging application timing requirements, and we propose to exploit the probabilistic real-time theory to achieve the required time predictability. After a brief recap of the fundamentals of this methodology, we focus on its applicability to HPC systems, to check their ability to satisfy such conditions. In particular, we studied the advantages of having heterogeneous processors in HPC nodes and how resource management affects the applicability of the proposed technique.

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Static WCET Analysis of GPUs with Predictable Warp Scheduling

Cited by 9 publications

References 17 publications

GPU Devices for Safety-Critical Systems: A Survey

GPU Devices for Safety-Critical Systems: A Survey

Sim-D: A SIMD Accelerator for Hard Real-Time Systems

Timing Predictability in High-Performance Computing With Probabilistic Real-Time

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