Statistical 3D Device Simulation of Full Fluctuations of Gate-All-Around Silicon Nanosheet MOSFETs at Sub-3-nm Technology Nodes

Kola, Sekhar Reddy; Li, Yiming; Chen, Chieh-Yang; Chuang, Min-Hui

doi:10.1109/vlsi-tsa54299.2022.9771002

Cited by 6 publications

(4 citation statements)

References 4 publications

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“…A flow of device fabrication for the explored GAA Si NS MOSFET with the origin of various random fluctuation sources including random nano-sized metal grains, random discrete dopants, and random interface trap fluctuations are shown in Fig. 1(b) [7].…”

Section: Device Simulation Fluctuation Sources and Data Generationmentioning

confidence: 99%

“…Due to the high surface-to-volume ratio, NS provides more drive current as compared to NW. Therefore, the GAA silicon (Si) NS metal-oxide-semiconductor field-effect transistor (MOSFET) has gained enormous attention as a promising candidate for a high degree scaling technology node [6], [7]. It exhibits excellent short channel control and improves the performance of the transistor at reduced gate length.…”

Section: Introductionmentioning

confidence: 99%

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A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

Butola

Kola

2022

IEEE Access

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The sensitivity of semiconductor devices to any microscopic perturbation is increasing with the continuous shrinking of device technology. Even the small fluctuations have become more acute for highly scaled nano-devices. Therefore, these fluctuations need to be addressed extensively in order to continue further device scaling. In this paper, we mainly focus on three intrinsic parameter fluctuation sources, work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF) for gate-all-around (GAA) silicon nanosheet (NS) MOSFETs. Generally, the effect of these fluctuations is analyzed using a time-consuming device simulation process. A machine learning (ML) based powerful and efficient artificial neural network (ANN) model is used to accelerate this process. Firstly, the effects of fluctuation sources are analyzed individually by using the ANN model and results have been presented that show the WKF variations dominate the threshold voltage (VTH), off-state current (IOFF), and on-state current (ION) variations among other fluctuation sources. Next, we examine the combined effect of all three fluctuation sources. It is crucial because considering only one fluctuation can result in unexpected variations due to other fluctuations present in the device. Therefore, the ANN model is used to estimate the combined effects as well. The results show that the proposed model predicts the outputs with an R 2 -score of 99% and an error rate of less than 1%. In addition, the ML is also utilized to calculate the permutation importance of input variables as a measure to investigate the contribution of each fluctuation source.

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Section: Device Simulation Fluctuation Sources and Data Generationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

Butola

Kola

2022

IEEE Access

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“…Problems arise at the front end of the line, such as local variability due to work function variation (WFV), line edge roughness (LER), and random dopant fluctuation (RDF). Furthermore, global variability issues, specifically critical dimension problems, are observed at the back end of the line [4][5][6][7][8]. These issues result in a wide distribution of electrical characteristics on wafers and lower yields.…”

Section: Introductionmentioning

confidence: 99%

Prediction of Statistical Distribution on Nanosheet FET by Geometrical Variability Using Various Machine Learning Models

Ha,

Kim,

Bang

et al. 2023

IEEE Access

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Due to the aggressive scaling down of logic semiconductors, the difficulty of semiconductor component processes has increased. As the structure of components becomes more complex, the time and cost of processes and simulations have risen. Machine learning is now being used to analyze the electrical characteristics data of semiconductor components and apply the trained machine learning to next-generation semiconductor development. Machine learning trained on process data and simulation results can quickly and accurately predict which electrical characteristics change significantly when the component's structure changes and which parameters have a significant impact on the electrical characteristic changes. This paper presents suitable machine learning models for analyzing and predicting the electrical characteristics (oncurrent (Ion), off-current (Ioff), threshold voltage (Vth), subthreshold swing (SS), and drain induced barrier lowering (DIBL)) and statistical distribution (mean and standard deviation of the electrical characteristics) resulting from geometrical variability (sheet thickness (Twire), sheet diameter (Dwire), oxide thickness (Tox), gate length (Lg), spacer length (Lsp), gate metal work-function (WF)) in nanosheet field-effect transistor (NSFET), which are a next-generation logic device. Machine learning models, including regulation-based models (Ridge, LASSO) and tree-based models (decision tree (DT), random forest (RF), extreme gradient boost (XGBoost), and light gradient boost machine (LGBM)), are trained on technology computer-aided design (TCAD) simulation data. The LGBM more accurately predicts the electrical characteristics and statistical distribution of the NSFET than the other models. Additionally, we analyze the effect of geometrical variability on the NSFET based on feature importance.

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“…In recent years, transistor scaling has been exemplified by Moore's Law, which has significantly increased the performance of devices [4,5]. However, in addition to the compelling advantages of cost reduction and performance enhancement, the continuous scaling of transistors has raised challenging issues concerning short-channel effects (SCE) and device reliability concerns [6][7][8]. Consequently, further transistor scaling has been hindered [9].…”

Section: Introductionmentioning

confidence: 99%

Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits

Kola,

2023

Preprint

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In this paper, we study the effect of parasitic channel on electrical characteristics and power consumptions of vertically stacked gate-all-around (GAA) silicon nanosheet (NS) MOSFETs of the bulk and silicon-on-insulator (SOI) substrates. Through deliberate control of the bottom parasitic channel coverage, we systematically assess its influence on DC, AC, and RF characteristics including power consumption. The observed findings highlight a significant differentiation among the bottom parasitic channels: GAA (i.e., control sample with 100% coverage), omega-shaped gate NS (70% and 80% coverages), and FinFET (60% coverage). Compared with the device with a 60% coverage channel, the device with a 100% coverage channel possesses 3520% and 8030% normalized leakage current improvement for both NFET and PFET under the bulk substrate, respectively. Compared with bulk-substrate devices, the SOI-substrate devices further significantly improve the leakage current. Due to enhanced off-state current leakages in the 100% covered bulk-substrate device, the static power demonstrates a notable improvement (about 98.1%), compared to 60% covered devices. Hence, the utilization of a 60% covered channel will result in a degradation of both device and circuit performance. The observation of GAA NS MOSFET indicates that an increase in the bottom parasitic channel coverage ratio leads to a positive impact on power consumption and leakage currents. The examination presented here is useful in the fabrication of stacked GAA NS MOSFETs.

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Statistical 3D Device Simulation of Full Fluctuations of Gate-All-Around Silicon Nanosheet MOSFETs at Sub-3-nm Technology Nodes

Cited by 6 publications

References 4 publications

A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

A Machine Learning Approach to Modeling Intrinsic Parameter Fluctuation of Gate-All-Around Si Nanosheet MOSFETs

Prediction of Statistical Distribution on Nanosheet FET by Geometrical Variability Using Various Machine Learning Models

Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits

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