Statistical Analysis and Design of HARP FPGAs

Wang, Gang; Sivaswamy, Satish; Ababei, Cristinel; Bazargan, Kia; Kastner, Ryan; Bozorgzadeh, Eli

doi:10.1109/tcad.2005.859485

Cited by 17 publications

(10 citation statements)

References 14 publications

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“…In FPGAs with bidirectional wire segments, some routing patterns in the design are more frequent than the others [8]. We obtained similar results for the FPGAs with unidirectional wire segments in our experiments.…”

Section: The Order Of Inputs For Switch Modules' Muxssupporting

confidence: 79%

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Improving bitstream compression by modifying FPGA architecture

Razavi

Zamani

2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation.

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Section: The Order Of Inputs For Switch Modules' Muxssupporting

confidence: 79%

“…All wire segments are unidirectional and they are either increasing or decreasing. To choose the best order for the MUX inputs, as in [8], we counted the routing patterns of routed MCNC benchmarks.…”

Section: The Order Of Inputs For Switch Modules' Muxsmentioning

confidence: 99%

Improving bitstream compression by modifying FPGA architecture

Razavi

Zamani

2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…According to Table I, dangling wires incur extra wire segments overhead in crossbar switches. Wang et al [2006] present the conflict between minimizing dangling wires and optimizing routing patterns (i.e., routability) in a partially hard-wired FPGA switch block design. However, dangling wires are inevitable in structured ASIC designs owing to metal wire pre fabrications.…”

Section: Switch Block Design Issuementioning

confidence: 99%

Routability optimization for crossbar-switch structured ASIC design

Tsai

Hsu

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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In the routing architecture of a structured application-specific integrated circuit (ASIC), the crossbar is one of the most area-efficient switch blocks. Nevertheless, a dangling wire occurs when there is a routing bend in a crossbar switch. Dangling wires incur longer wire lengths as well as a higher interconnection capacitance. In this article, we tackle dangling wire issues for structured ASIC routability optimization. We first propose a compact graph model for crossbar-switch routing. With our graph model, switch connectivity relations can be removed to keep the 2D structured ASIC routing graph efficient and to speed up the runtime of our routing algorithm. Furthermore, we propose a heuristic dangling-wire-avoidance routing framework containing deferred pin assignment, Steiner point reassignment, and anchor pair insertion in order to minimize dangling wires and channel width. Finally, in order to take routing bends and channel width into account simultaneously, we propose concurrent and sequential integer linear programming (ILP) formulations and ILP variable/constraint degeneration techniques. The experimental results demonstrate that our proposed heuristic routing framework reduces dangling wires by 19%, channel width by 38%, and wire length by 13% to VPR using the crossbar switch (VPR-C). In addition, our sequential ILP router reduces dangling wires by 38%, channel width by 40%, and wire length by 15% compared to VPR-C. Thus, the runtime efficiency of our sequential ILP router is attractive for crossbar-switch structured ASIC routing.

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“…Wang et al [24] replaced some programmable wires in the FPGA routing fabric with HArdwired Routing Patterns (HARPs), which reduced delay and power consumption, but limit flexibility. The FPCA architectures described here attempt to use HARPs in a more systematic fashion, which is feasible because the application domain is limited to compressor trees.…”

Section: Related Workmentioning

confidence: 99%

“…The design of the FPCA CSlice, starting with FPCA-1.1, was motivated by prior work on HARPs in FPGAs [24]. A HARP is a direct connection in the routing network that bypasses switch boxes at routing intersections.…”

Section: Cslice Design and Integrationmentioning

confidence: 99%

Architectural improvements for field programmable counter arrays

Cevrero

Athanasopoulos

Parandeh-Afshar

et al. 2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA; the remaining portion of the circuit is synthesized on the FPGA. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60× and 2.40× on a set of arithmetic benchmarks.

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Statistical Analysis and Design of HARP FPGAs

Cited by 17 publications

References 14 publications

Improving bitstream compression by modifying FPGA architecture

Improving bitstream compression by modifying FPGA architecture

Routability optimization for crossbar-switch structured ASIC design

Architectural improvements for field programmable counter arrays

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