Statistical analysis and modeling for error composition in approximate computation circuits

Chan, Wei-Ting Jonas; Kahng, Andrew B.; Kang, Seokhyeong; Kumar, Rakesh; Sartori, John

doi:10.1109/iccd.2013.6657024

Cited by 48 publications

(21 citation statements)

References 21 publications

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“…Such additive error models have been used in fixed-point quantization noise analy sis [ 18]. The work in [1,7] also adopts this model. Fig.…”

Section: Error Analysismentioning

confidence: 99%

“…error PMFs of various operation units without any further simuDating back to traditional fixed-point conversion, simulation-lation overhead, and this is a main difference from existing work based or analytical approaches have been used for quality es-in [ 1,6]. The use of general PMFs allows for translation into a timation.…”

mentioning

confidence: 98%

“…Only limited work exists overcoming these limitations. Recent approaches first characterize error behavior of individual hardware operators by simulation, and then ana lytically propagate either a derived quality metric [1] or input data and error probability mass functions (PMFs) [6]. These approaches work with various approximation types and quality metrics, but still depend on exhaustive simulation to character ize individual unit error behavior.…”

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confidence: 99%

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Statistical quality modeling of approximate hardware

Lee

Han

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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Beyond traditional bit truncation, recently pro posed arithmetic and logic approximations have enriched the quality versus energy design space for custom hardware kernels in signal processing and other error-tolerant applications. Sys tematic exploration of such trade-offs requires fast, accurate, and generic quality-energy models that can drive datapath opti mizations. Existing quality estimation approaches, however, are either based on slow simulation or limited in supported approx imation types and quality metrics. In this paper, we propose a novel semi-analytical quality model that can predict a wide range of statistical metrics for arbitrary hardware approxima tions with deterministic error behavior. Input and error depen dencies are captured using one-time error-free simulation only. Combining our quality estimation with a faithful energy model considering both switching activity and voltage scaling, we pro vide a complete quality-energy optimization flow. Optimization results for FFT and IDCT benchmarks show that our approach is 28x faster than purely simulation-based exploration, and 2x faster than existing hybrid approaches, all while achieving com parable estimation accuracy.

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“…Such additive error models have been used in fixed-point quantization noise analy sis [ 18]. The work in [1,7] also adopts this model. Fig.…”

Section: Error Analysismentioning

confidence: 99%

mentioning

confidence: 98%

mentioning

confidence: 99%

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Statistical quality modeling of approximate hardware

Lee

Han

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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“…In [25], a systematic methodology is presented for automatic logic synthesis of approximate circuits, that synthesizes an approximate version of a given RTL specification for a given quality constraint. A statistical error analysis and model is presented in [26] and [27].…”

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confidence: 99%

“…Recently approximate circuits have been proposed in [19][20][21][22][23][24][25][26][27] which also reduce area, latency and power.…”

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confidence: 99%

Image processing using approximate datapath units

Vasudevan

Chakrabarti

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in [23] and [24]. First, we show how choice of algorithm and parallel adder design can be used to implement 2D Discrete Cosine Transform (DCT) algorithm with good performance but low area. Our implementation of the 2D DCT has comparable PSNR performance with respect to the algorithm presented in [23] with ~35-50% reduction in area. Next, we use the approximate 2x2 multiplier presented in [24] to implement parallel approximate multipliers. We demonstrate that if some of the 2x2 multipliers in the design of the parallel multiplier are accurate, the accuracy of the multiplier improves significantly, especially when two large numbers are multiplied. We choose Gaussian FIR Filter and Fast Fourier Transform (FFT) algorithms to illustrate the efficacy of our proposed approximate multiplier. We show that application of the proposed approximate multiplier improves the PSNR performance of 32x32 FFT implementation by 4.7 dB compared to the implementation using the approximate multiplier described in [24]. We also implement a state-of-the-art image enlargement algorithm, namely Segment Adaptive Gradient Angle (SAGA) [29], in hardware. The algorithm is mapped to pipelined hardware blocks and we synthesized the design using 90 nm technology. We show that a 64x64 image can be processed in 496.48 µs when clocked at 100 MHz. The average PSNR performance of our implementation using accurate parallel adders and multipliers i is 31.33 dB and that using approximate parallel adders and multipliers is 30.86 dB, when evaluated against the original image. The PSNR performance of both designs is comparable to the performance of the double precision floating point MATLAB implementation of the algorithm. This work is also affectionately dedicated to the six different computers that were used to complete this work.

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