2007
DOI: 10.1016/j.microrel.2007.07.079
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Statistical analysis during the reliability simulation

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Cited by 19 publications
(6 citation statements)
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“…Reliability and safety analysis is conducted by evaluating automatically generated fault trees (FT) or reliability block diagrams (RBD). Bestory et al 9 describe electronic circuit behavior and component-based degradation models in VHDL-AMS and performs statistical reliability analysis using Monte-Carlo-Simulations over lifetime.…”
Section: Modeling System Behavior and Reliabilitymentioning
confidence: 99%
“…Reliability and safety analysis is conducted by evaluating automatically generated fault trees (FT) or reliability block diagrams (RBD). Bestory et al 9 describe electronic circuit behavior and component-based degradation models in VHDL-AMS and performs statistical reliability analysis using Monte-Carlo-Simulations over lifetime.…”
Section: Modeling System Behavior and Reliabilitymentioning
confidence: 99%
“…3 illustrates how a failure density function w θ [k] is fitted with a generalized extreme value (GEV) distribution, indicating the failure-time distribution of the circuit. In contradiction to [3], this work uses a SPICE-netlist-based reliability simulation (see section III) to analyze the failure rate. This provides a more accurate and detailed picture of how a circuit will behave under degradation, especially for nanometer CMOS where short-channel effects are emerging.…”
Section: Variability-aware Reliability Simulationmentioning
confidence: 99%
“…1. Bestory et al [3] used behavioral circuit models to calculate the circuit reliability under process variations. This approach, although it is fast, lacks accuracy especially in nanometer CMOS when short-channel effects, usually not included in behavioral models, come into play.…”
Section: Introductionmentioning
confidence: 99%
“…The latter is activated by the stress applied on the cell during its life time (erasing, programing, temperature variations, etc.). One of the major issues is the global cost of such studies [2]. One solution lies in specific device test structures integrated in the same technology as the final product.…”
Section: Introductionmentioning
confidence: 99%