Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs

Tang, Yongjian; Hegt, Hans; Roermund, Arthur van; Doris, Kostas; Briaire, J.

doi:10.1109/iscas.2007.378331

Cited by 12 publications

(5 citation statements)

References 3 publications

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“…The integration result can be rewritten to (2), where d e is the timing error after calibration. The definition of d R and d D can be found in Fig.…”

Section: B Measurement Methodsmentioning

confidence: 99%

“…Exemplary implementation of a VDL using digital control [4] Since the reference current cell has a fixed output amplitude, only unary current cells can be calibrated. In the case of a segmented DAC with a certain minimum segmentation, it can be shown that the timing errors of the binary current cells have a negligible impact on the total dynamic performance [2]. Alternatively, in [4], it is suggested to calibrate the timing of all binary current cells plus one dummy LSB with one VDL.…”

Section: Vmentioning

confidence: 99%

“…Spurious Free Dynamic Range (SFDR), degrades for high frequency input signals. One cause for this degradation is the nonidentical switching behavior of the unit elements, according to [2]. Causes for non-identical switching behavior include: unbalances and mismatches in the clock distribution, data distribution and output networks, mismatch in the switching transistors and other non-idealities.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Timing error measurement for highly linear wideband Digital to Analog Converters

Bechthum

Tang

Hegt

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-The switching characteristics of Digital to Analog Converter (DAC) unit elements can limit DAC dynamic performance at high speeds [1]. Unbalances and mismatches in clock, data and output networks create a non-identical environment for every current cell. Together with mismatch in current cell switching transistors and other non-idealities, this causes the switching characteristics of the current cells to be non-identical.A new method for measuring the timing error is presented. The measurement method is shown to be insensitive to all important non-idealities in the DAC and the measurement circuit. Transistor level simulations show that the measurement accuracy is better than 125fs. Together with an ideal calibration loop, this measurement accuracy can lead to an average SFDR of more than 95dB when applied to an exemplary 12 bit 1GSps DAC.

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“…The integration result can be rewritten to (2), where d e is the timing error after calibration. The definition of d R and d D can be found in Fig.…”

Section: B Measurement Methodsmentioning

confidence: 99%

Section: Vmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Timing error measurement for highly linear wideband Digital to Analog Converters

Bechthum

Tang

Hegt

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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“…The principle of mapping calibration techniques is digitally optimizing the switching sequence so that the integral nonlinear error is minimized. Existing mapping techniques, such as static-mismatch mapping (SMM) [10]- [13] and timing error mapping [15], [16] can only optimize the switching sequence based on single kind of error, either amplitude or timing. However, the DAC linearity is determined by both amplitude and timing errors, especially at high frequencies.…”

Section: A Traditional Mappingmentioning

confidence: 99%

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

Tang

Briaire

Doris

et al. 2011

IEEE J. Solid-State Circuits

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“…The nonlinearity and spurious-free dynamic range (SFDR) of DACs have been studied extensively [10], [11], [12], [13], [14], [15]. This paper focuses on the relation between the DAC nonlinearity and ACPR.…”

Section: Introductionmentioning

confidence: 99%

Relation Between INL and ACPR of RF DACs

Babamir

Razavi

2022

IEEE Trans. Circuits Syst. I

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Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs

Cited by 12 publications

References 3 publications

Timing error measurement for highly linear wideband Digital to Analog Converters

Timing error measurement for highly linear wideband Digital to Analog Converters

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

Relation Between INL and ACPR of RF DACs

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