Statistical Analysis of Threshold Voltage Variation Using MOSFETs With Asymmetric Source and Drain

Ichino, Shinya; Teramoto, Akinobu; Kuroda, Rihito; Mawaki, Takezo; Suwa, Tomoyuki; Sugawa, Shigetoshi

doi:10.1109/led.2018.2874012

Cited by 5 publications

(3 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The physical structure mesh simulation is developed for a P-type silicon with the employment of substrate orientation at <100> for which is followed by the formation of the oxide layer on the silicon bulk that is purposed as mask during the implantation of P-well. Subsequent to the gate terminal that is secluded from both source and drain, for which opposes the conductive channel by a dielectric layer, Boron is infused into the silicon substrate for 1x10 17 atom/cm 3 before the gate oxide is established for 870 o C with 3% of hydrochloric acid (HCl) in dry oxygen condition at 1 atmospheric pressure. Subsequently, the variation in threshold voltage can also be achieved with Boron implanted for 1.95x10 13 atom/cm 3 with 5 KeV of energy in the channel region.…”

Section: Device Fabricationmentioning

confidence: 99%

Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device

Roslan¹,

Salehuddin²,

Zain³

et al. 2022

JMechE

View full text Add to dashboard Cite

In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness of the process parameters towards four output responses such as threshold voltage (VTH), drive current (ION), leakage current (IOFF) and Subthreshold Swing (SS). The virtual fabrication of the 16 nm double-gate fin FET was performed using ANTHENA module while the electrical characteristics of the device were simulated using ATLAS module. These two modules were combined with Taguchi method to aid in designing and optimizing the process parameters. The electrical characterization was performed and significant improvement could be seen on the TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.03106 and 3.61106 respectively for 0.179±12.7% V of VTH. It can be observed that when approaching a higher value of dielectric constant (high-K), the ION increases while the SS and IOFF decreases. As conclusion, the output responses from high-K materials have been proven to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015.

show abstract

Section: Device Fabricationmentioning

confidence: 99%

Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device

Roslan¹,

Salehuddin²,

Zain³

et al. 2022

JMechE

View full text Add to dashboard Cite

show abstract

“…The physical parameters of the materials were referenced from previous studies [19]- [22]. In this study, the constant current method was used to extract threshold voltage at ID = 1µA [23]. The simulations were conducted using Synopsys' Sentaurus technology computer-aided design (TCAD).…”

Section: Introductionmentioning

confidence: 99%

A Novel Structure Between WL Spaces to Improve the Retention Characteristics in 3D NAND Flash

Suh,

Kyung,

Jung

et al. 2024

IEEE Access

View full text Add to dashboard Cite

As NAND flash evolved from two-dimensional (2D) to three-dimensional (3D), all cells have been changed to share a charge trap layer (CTL). This change has a lateral charge spreading effect, which is the trapped charge spreading laterally. This lateral charge spreading effect causes a major problem in NAND flash reliability. In this study, we introduce a new structure that can improve lateral charge spreading by defining a new parameter called 'intercell CTL thickness' and modifying the CTL structure in the WL spaces. When the intercell CTL thickness decreases, the ISPP slope remains relatively constant up to a certain thickness, indicating that program efficiency does not decrease until that critical point. However, as the intercell CTL thickness decreases, the current also decreases, which can be explained by the screen effect and dielectric constant reduction. As for the thickness of the CTL, which is the trap nitride thickness, it decreases while the oxide thickness increases. As a result, it causes a decrease in the total dielectric constant, resulting a decrease in cell current. In addition, as the physical CTL thickness decreases, more charges will be trapped in the same VTH condition. More charges strengthen the screen effect on the electric field, causing a decrease in cell current. In this study, we will discuss the retention characteristics of this novel structure, investigate the window characteristics between lateral charge spreading with cell current, and propose the optimal point.

show abstract

“…The challenges however prevailed in defining the electrical characterization off the variations of the process parameter [11]. The enhancement of design processes in the Polysilicon/Silicon Dioxide (PolySi/SiO2)-based DG-FinFET can be furthered in terms of its robustness through the variations of statistical method that have been implemented in numerous Nano engineering designs [12][13][14][15][16][17][18]. The process parameters have been optimized through the application of Taguchi method by Salehuddin et al and Afifah et al The aforementioned authors have highlighted the optimization of both VTH and IOFF for a 45 nm besides lowering the IOFF whilst nominalized the VTH for a 22 nm design [19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method

Roslan

Salehuddin

Zain

et al. 2020

IJEECS

View full text Add to dashboard Cite

The impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (ION), leakage current (IOFF), and threshold voltage (VTH) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose, VTH doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards ION and IOFF. The most dominant factor procured is the polysilicon doping tilt. The ION and IOFF obtained after the optimization are 1726.88 μA/μm and 503.41 pA/μm for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013.

show abstract

Statistical Analysis of Threshold Voltage Variation Using MOSFETs With Asymmetric Source and Drain

Cited by 5 publications

References 26 publications

Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device

Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device

A Novel Structure Between WL Spaces to Improve the Retention Characteristics in 3D NAND Flash

Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method

Contact Info

Product

Resources

About