In this paper, the effect of heavy ion irradiation on 65 nm bulk silicon MOS devices is experimentally investigated. Different performance degradation behaviour is observed due to the intrinsic random incident of heavy ions. After irradiation, the threshold voltage (V th ) shifts negatively and the largest V th shift is 54 mV. The drain induced barrier lowing (DIBL) effect deteriorates and DIBL increases by more than 30 mV V −1 . The variation of maximum transconductance (G m ) is up to 30%. The off-state leakage current (I off ) increases by several times, up to one order of magnitude. These performance degradation is attributed to the displacement damage in the active region, interface states at gate oxide interface and trapped charges in shallow trench isolation (STI) induced by micro-dose effect. Moreover, statistical analysis on the geometry dependence is firstly demonstrated. The average value of V th shift, DIBL shift, and I off degradation increase with the decrease of gate width. Finally, the influence of technology downscaling from deep-submicron to nanoscale on the heavy ion irradiation effect is statistically analyzed. Four technology nodes (65 nm, 90 nm, 0.18 μm and 0.25 μm) are chosen for comparison. The results indicates that the V th shift and DIBL shift increase with the technology downscaling. The I off degradation is strongly correlated with the trapped charge in STI caused by micro-dose effect. The results are helpful to further understand the single event effects of nanoscale bulk silicon MOS devices and may provide guideline for radiation-hardened design.