Statistical-aware designs for the nm era

Abstract

As technology scaled beyond the 100nm node, process variation and particularly random variations effects have had significant impact on the design yield. Memory designs, namely SRAMs, have become more prone to fails. Dynamic stability and dynamic noise margins have become a serious concern. Several design methodologies have been proposed to analyze and counter process variations. In this paper, we revisit key variabilitydriven design contributions, in terms of dual supply techniques, bitline clamping methods, and novel circuits with programmable capabilities, with particular emphasis on statistical exploration of the design space.

Statistical approach to low power and high volume Pineview Atom-based SoC design

“…Larger die, especially for multiple-core chip, may require more IDVs and Ring oscillators. The process variations [1,2] are caused by, say, deviation of transistor size which is physically limited and does not shrink well as the transistor size itself. Larger deviation of the transistor characteristics, e.g., device delay and its leakage power, is usually addressed by design for worst-case which becomes unacceptable for high volume, low power and high performance chips.…”

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

“…Hence, dual supply techniques combining a low logic power supply with a slightly higher SRAM power supply to improve cell stability are one method to overcome large leakage and counter process variation [19]. In addition, repair techniques such as redundancy and error checking and correcting (ECC) are applied to reduce cell failure rate and improve V min [20].…”