Statistical circuit characterization for deep-submicron CMOS designs

Chen, J.; Orshansky, Michael; Hu, Chenming; Wan, C.-P.

doi:10.1109/isscc.1998.672388

Cited by 7 publications

(4 citation statements)

References 7 publications

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“…In addition, the accuracy of the MC approach depends on the accuracy of the variations of the SPICE model parameters. The latter accuracy can be improved with greater attention paid to the ET variation data [15]. Principal component analysis (PCA) was introduced to capture the complex correlations of device parameters [16].…”

Section: Challenges In Statistical Optimized Design Methodologymentioning

confidence: 99%

A Process Variation Tolerant OTA Design for Low Power ASIC Design

Benschwartz¹,

Sakthivel²

2016

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Technology development and continuous down scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology for process variability aware design by incorporating the major challenge of statistical circuit performance relating the device and circuit level variation in an accurate and efficient manner to improve the reliability, robustness and stability of the circuit. The device sensitive parameters are identified and accurately quantified by continuous realistic assessments using statistical methods. The modularity of the methodology can be validated by the output performance obtained from the gain and phase response of OTA which is highly stable when subjected to worst case process variation scenario. In the proposed optimization, the circuit is strengthened by fixing the optimum aspect ratio without adding any additional compensation devices complicating the circuit resulting in low power consumption of only 0.116 mW in standard CMOS 0.18 µm technology with 1.8 V power supply.

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Section: Challenges In Statistical Optimized Design Methodologymentioning

confidence: 99%

A Process Variation Tolerant OTA Design for Low Power ASIC Design

Benschwartz¹,

Sakthivel²

2016

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“…The main feature of DSM is the insistence that all sampled device characteristics from a test die be kept as a set, and be directly applied to all further analysis. No statistical operation is performed that can inadvertently lead to the effect of averaging out the device fluctuations arising from different mechanisms, which can happen if principal component analysis or factorial analysis are used [5]. In DSM a statistically significant number of dies is sampled and kept as a set that typically contains the device I-V parameters, and gate, overlap, junction, and interconnect capacitances.…”

Section: Methodsmentioning

confidence: 99%

“…This approach reduces the number of device parameters under consideration using principal component analysis (PCA), and then employs response surface methodology to generate the statistical circuit performance characteristics. However, the use of PCA on device parameters from the deep sub-micron technologies is undesirable because it may fail to capture the complex correlations of the device parameters [5]. This is due to the fact that for the deep sub-micron CMOS technologies a combination of device physics, die locationdependence, optical proximity effect, microloading in etching and deposition, etc., may lead to heterogeneous and nonmonotonic relationships among the device parameters that cannot be captured by the PCA-based device parameter characterization.…”

Section: Introductionmentioning

confidence: 99%

“…It does not employ any statistical techniques that may lead to the inadvertent loss of parameter correlations arising from the complex physical processing of the deep submicron technologies. This is accomplished with a directsampling method [5]. In order to avoid a large number of simulations of the whole circuit, and thus overcome the deficiency of Monte-Carlo based methods, it constructs a circuit model in terms of performance variables of the simpler blocks constituting the circuit.…”

Section: Introductionmentioning

confidence: 99%

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A statistical performance simulation methodology for VLSI circuits

Orshansky

Chen

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.

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The impact of gate oxide scaling (3.2–1.2 nm) on sub-100 nm complementary metal-oxide-semiconductor field-effect transistors

Yeh

Lin

2002

Thin Solid Films

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Statistical circuit characterization for deep-submicron CMOS designs

Cited by 7 publications

References 7 publications

A Process Variation Tolerant OTA Design for Low Power ASIC Design

A Process Variation Tolerant OTA Design for Low Power ASIC Design

A statistical performance simulation methodology for VLSI circuits

The impact of gate oxide scaling (3.2–1.2 nm) on sub-100 nm complementary metal-oxide-semiconductor field-effect transistors

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