Statistical gate sizing for timing yield optimization

Sinha, Debjit; Shenoy, Narendra; Zhou, Hai

doi:10.1109/iccad.2005.1560214

Cited by 54 publications

(55 citation statements)

References 7 publications

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“…This can lead to severe over-design in term of area, power, circuit timing, and design time [7]. Finally, corner-based STA computation is very expensive because it requires a large number of corner cases.…”

Section: A Timing Analysismentioning

confidence: 99%

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Kim

Walker

2006

Seventh International Workshop on Microprocessor Test and Verification (MTV'06)

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Chair of Advisory Committee: Dr. Duncan Moore Henry Walker As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology.In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated.Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.

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Section: A Timing Analysismentioning

confidence: 99%

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Kim

Walker

2006

Seventh International Workshop on Microprocessor Test and Verification (MTV'06)

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“…Early work 37) , proposes formulation of statistical objective and timing constraints, and solves the resulting nonlinear optimization formulation. In other works on robust gate sizing 5),19),20), 82) , the central idea is to capture the delay distributions by performing a statistical static timing analysis (SSTA), as opposed to the traditional STA, and then use either a general nonlinear programming technique or statistical sensitivity-based heuristic procedures to size the gates. In other work 69) , the mean and variances of the node delays in the circuit graph are minimized in the selected paths, subject to constraints on delay and area penalty.…”

Section: Statistical Circuit Optimizationmentioning

confidence: 99%

Variability and Statistical Design

Sapatnekar

2008

IPSJ Transactions on System LSI Design Methodology

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With each technology generation, the effects of on-chip variations are seen to more profoundly affect digital circuit behavior. These variations may arise from fluctuations attributed to the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield, as well as variations in the environmental operating conditions (e.g., supply voltage or temperature) after the circuit is manufactured, which impact the performance of the design. These effects can cause unacceptable alterations in circuit performance parameters such as timing and power, and variation-tolerant design is imperative for next-generation designs. This paper overviews research in this area, describing methods for the analysis and optimization of statistical effects.

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“…The continuous semiconductor technology scaling leads to growing process variations (Agarwal & Nassif, 2007), and statistical optimization has been actively researched to cope with process variations. Recent examples include stochastic gate sizing for power reduction (Bhardwaj & Vrudhula, 2005;Mani et al, 2005) and for yield optimization (Davoodi & Srivastava, 2006;Sinha et al, 2005), stochastic buffer insertion to minimize clock delay , and adaptive body biasing with post-silicon tuning (Mani et al, 2006). However, all these papers ignore operation variation such as crosstalk difference over input vectors, power supply noise fluctuation over time, and processor temperature variation over workload.…”

Section: Introductionmentioning

confidence: 99%