Statistical interconnect metrics for physical-design optimization

Agarwal, Kanak; Agarwal, Mridul; Sylvester, Dennis; Blaauw, David

doi:10.1109/tcad.2005.855954

Cited by 48 publications

(28 citation statements)

References 33 publications

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“…For example, Table I (see Section II) shows common BEOL corners in which the wire width (∆W ), wire thickness (∆T ) and dielectric thickness (∆H) variations are biased to the minimum or maximum values. 1 Although BEOL parameters have strong spatial correlations within a die [12], different BEOL parameters are not fully correlated [5] [6] [10] [13] [22]. When the parameters are not fully correlated, the likelihood of a worstcase (or best-case) condition on all layers is vanishingly small (if not a physical impossibility).…”

Section: Introductionmentioning

confidence: 99%

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Improved signoff methodology with tightened BEOL corners

Chan

Dobre

Kahng

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-To ensure functional correctness, conventional chip implementation methodology signs off the SOC design at extreme process, voltage and temperature (PVT) conditions. At the 20nm node and beyond, the back end of line (BEOL) layers have become major sources of variation, which must be accounted for by signoff at various BEOL corners. Conventional signoff methodology uses extreme BEOL corners, in which all BEOL layers are skewed to the worst-case condition (e.g., all BEOL layers have the worst parasitic capacitance). However, such a BEOL condition is very pessimistic because the probability of having all BEOL layers skew towards the worst-case condition simultaneously is extremely small. Such pessimism results in longer chip implementation schedules and poorer design quality. In this paper, we propose a signoff methodology with tightened BEOL corners to recover the pessimism incurred by the conventional BEOL corners. This approach is based on the observation that most timing-critical paths use different BEOL layers. When the variations of BEOL layers are not fully correlated, the BEOL-induced timing variation is much smaller due to averaging of random variations. Our experimental results show that by using tightened BEOL corners, we can reduce timing-violation paths by up to 100% and improve the WNS and TNS by up to 101ps and 53ns, respectively.

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Section: Introductionmentioning

confidence: 99%

“…To reduce the pessimism in CBCs, various statistical RC extraction and timing analysis methods have been proposed [1] [2] [3]. The main drawback of statistics-based methods is the lack of availability of commercial EDA tools to characterize a RC variation model (e.g., sensitivities of RC to BEOL physical parameters).…”

Section: Introductionmentioning

confidence: 99%

Improved signoff methodology with tightened BEOL corners

Chan

Dobre

Kahng

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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“…geometric parameters are useful for diverse variability modeling techniques. They are necessary for establishing the parameterized system description in various variation-aware techniques, such as the moment-based timing analysis [7], the Hermite polynomial based statistic analysis [8] and the parametric Model Order Reduction (pMOR) technique proposed in [9]. The sensitivities have been incorporated in the Standard Parasitic Exchange Format (SPEF) [10].…”

Section: Introductionmentioning

confidence: 99%

Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique

Graaf

Meijs

2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

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Abstract-This paper presents a useful extension for an existing algorithm of capacitance sensitivity computation with respect to multiple geometric variations. The existing algorithm is applicable for BEM-based capacitance extraction tools and provides good accuracy results. Using the Schur complement technique, the extended algorithm can achieve an even better accuracy at a modest increase of computational cost. With such extension, the enhanced algorithm becomes more flexible in the sense that it is able to provide different solutions for different application requirements: high efficiency with good accuracy or high accuracy with modest time cost.

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“…These sensitivities are necessary for establishing basic formulations in various variation-aware algorithms, such as moment-based timing analysis [1], Hermite polynomial based statistic analysis [2] and parametric Model Order Reduction (pMOR) proposed in [3]. Also, techniques including fast corner generation, multi corner extraction and the variation-aware Static Timing Analysis (STA) presented in [4] are all based on sensitivity models.…”

Section: Introductionmentioning

confidence: 99%

Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors

Kolk

Meijs

2009

2009 IEEE Custom Integrated Circuits Conference

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Abstract-The on-going reduction of the on-chip feature size goes together with an increase of process variability. While the manufacturer is expected to improve the uniformity of its output, and the designers are expected to enhance circuit adaptability and reliability, the design tools are expected to deliver convenient and fast approaches capable of giving accurate characterizations of manufacturing tolerances. In this paper, we present an algorithm that enables an extension of 3-D capacitance extractors to generate both the nominal capacitances and their sensitivities w.r.t. all geometric parameters with only one extraction. Using the domaindecomposition technique, it is shown that sensitivities can be derived from the intermediate data of the standard capacitance extraction using the Boundary Element Method (BEM). The algorithm has been implemented in a layout-to-circuit extractor. It is shown by experiments that the additional cost for the sensitivity computation is less than 20% of the standard time consumption, essentially independent of the number of parameters.

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Statistical interconnect metrics for physical-design optimization

Cited by 48 publications

References 33 publications

Improved signoff methodology with tightened BEOL corners

Improved signoff methodology with tightened BEOL corners

Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique

Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors

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