Statistical reliability analysis under process variation and aging effects

Abstract

Abstract-Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliability. Various aging effects, such as negative bias temperature instability, cause continuous performance and reliability degradation during circuit run-time usage. In this work, we present a statistical analysis framework that characterizes the lifetime reliability of nanometer-scale integrated circuits by jointly considering the impact of fabrication-induced process variation and run-time aging effects. More specifically, our work focuses on characterizing circuit threshold voltage lifetime variation and its impact on circuit timing due to process variation and the negative bias temperature instability effect, a primary aging effect in nanometer-scale integrated circuits. The proposed work is capable of characterizing the overall circuit lifetime reliability, as well as efficiently quantifying the vulnerabilities of individual circuit elements. This analysis framework has been carefully validated and integrated into an iterative design flow for circuit lifetime reliability analysis and optimization.

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

“…Time-0 process variation affects not only power and performance characteristics at time-0, but also the rate of aging [22], [23]. This may cause each transistor to age at different rate.…”

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

“…They differ in the type of reliability effects considered and the type of circuits studied. For digital circuits, NBTI-aware statistical timing analysis considering process variations are proposed in (Vaidyanathan, Oates, Xie & Wang, 2009), ), (Wang et al, 2008) and (Lu et al, 2009). Authors in (Vaidyanathan, Oates, Xie & Wang, 2009) build up gate-level delay fall-out model by propagating the device parameter fall-out model due to NBTI and process variations into the gate delay model.…”

“…Using variation-aware gate delay model, the timing behavior of a path is modeled in (Wang et al, 2008). Authors in (Lu et al, 2009) apply the NBTI aging-aware statistical timing analysis into circuit level. All of those methods rely on the analytical expression of performance features, which is suitable for digital circuits but difficult in analog domain.…”

Context aware slope based transistor-level aging model

“…The delay models are commonly based on the Sakurai's a power law MOSFET model [1], to express the transistor current, which does not take into account the prevalent effects characteristic for present nanometer technologies. Moreover, most papers do not model the joint effect of multiple aging mechanisms [12][13][14][15], and very few consider the aged signal slope [2] as wearout monitor. In [3], the authors propose a delay model considering both Time Dependent Dielectric Breakdown (TDDB) and Negative Bias Temperature Instability (NBTI).…”