Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

Narayanan, Rajeev; Seghaier, Ibtissem; Zaki, Mohamed H.; Tahar, Sofiène

doi:10.1109/tvlsi.2012.2219083

Cited by 6 publications

(4 citation statements)

References 15 publications

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“…To improve the coverage of analog circuits state space, the authors in [12] proposed an algorithm that guides the input stimuli but falls short to address the effect of Process Variation (PV). In [9], the PLL is modeled using Stochastic Differential Equations (SDE). Then, it is verified using a statistical runtime verification approach that combines Monte Carlo/Bootstrap techniques with hypothesis testing.…”

Section: Related Workmentioning

confidence: 99%

“…Then, it is verified using a statistical runtime verification approach that combines Monte Carlo/Bootstrap techniques with hypothesis testing. The accuracy of the verification technique is directly related to the confidence level which depends on the number of simulation runs [9]. In addition, this technique introduces randomness in the simulation but fails to cover all possible design behaviors.…”

Section: Related Workmentioning

confidence: 99%

“…If the phase difference between the reference signal and the feedback one is within the tolerated bound [−0.2 • , 0.2 • ], then the PLL is "locked", otherwise the PLL is "not locked". The PLL locking property in ESRE form is given in Equation (9). Table 1.…”

Section: Verification Of the Locking Propertymentioning

confidence: 99%

See 2 more Smart Citations

A qualitative simulation approach for verifying PLL locking property

Seghaier

Aridhi

Zaki

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Simulation cannot give a full coverage of Phase Locked Loop (PLL) behavior in presence of process variation, jitter and varying initial conditions. Qualitative Simulation is an attracting method that computes behavior envelopes for dynamical systems over continuous ranges of their parameters. Therefore, this method can be employed to verify PLLs locking property given a model that encompasses their imperfections. Extended System of Recurrence Equations (ESREs) offer a unified modeling language to model analog and digital PLLs components. In this paper, an ESRE model is created for both PLLs and their imperfections. Then, a modified qualitative simulation algorithm is used to guarantee that the PLL locking time is sound for every possible initial condition and parameter value. We used our approach to analyze a Charge Pump-PLL for a 0.18μm fabrication process and in the presence of jitter and initial conditions uncertainties. The obtained results show an improvement of simulation coverage by computing the minimum locking time and predicting a non locking case that statistical simulation technique fails to detect.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A qualitative simulation approach for verifying PLL locking property

Seghaier

Aridhi

Zaki

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

Self Cite

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show abstract

“…A method for the design modification and verification of analog circuit was discussed [21], the method utilizes the previous circuit simulation results to the successive changed circuit analysis, and the method can be used for the verification of linear and nonlinear analog circuit. The verification techniques when there are shot noise, thermal noise and process variations in the analog circuits were investigated [22], the stochastic differential equations were used to model these noises.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

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Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models

Selvaraj

Wanjale²

2017

2017 25th International Conference on Systems Engineering (ICSEng)

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Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

Cited by 6 publications

References 15 publications

A qualitative simulation approach for verifying PLL locking property

A qualitative simulation approach for verifying PLL locking property

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models

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