Statistical timing analysis using bounds and selective enumeration

Agarwal, Aseem; Zolotov, Vladimir; Blaauw, David

doi:10.1109/tcad.2003.816217

Cited by 119 publications

(46 citation statements)

References 28 publications

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“…Formulation (12) is a stochastic optimization problem. The statistical analysis and design of digital circuits is an area of growing interest and importance; see, e.g., Agarwal et al (2003), Bhardwaj et al (2003), Brambilla and Maffezzoni (2001), Jyu et al (1993), Orshansky et al (1999), and Orshansky and Keutzer (2002). This is still an active research area, and no consensus has emerged as to what the best statistical models are.…”

Section: Statistical Designmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Statistical Designmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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“…Major algorithms of SSTAs-Block based [3], [5]- [7] and Path based [8]- [10] approaches are presented. Path based technique evaluates the timing constraints of the paths between the blocks in a design in topological order.…”

Section: Introductionmentioning

confidence: 99%

A Fully Pipelined Power-Optimization Implementation of Monte Carlo Based SSTA on FPGA

Rao¹

2013

IOSR-JVSP

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“…Substantial work has been done in the area of analysis, estimation and optimization of statistical static timing [2], [4], [5], [6], [7], [8] but statistical leakage power measurement and optimization is still emerging [3], [9], [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Accurate estimation of vector dependent leakage power in the presence of process variations

Fernandes

Vemuri

2009

2009 IEEE International Conference on Computer Design

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Abstract-With the increasing importance of run-time leakage power dissipation (around 55% of total power), it has become necessary to accurately estimate it not only as a function of input vectors but also as a function of process parameters. Leakage power corresponding to the maximum vector presents itself as a higher bound for run-time leakage and is a measure of reliability. In this work, we address the problem of accurately estimating the probabilistic distribution of the maximum runtime leakage power in the presence of variations in process parameters such as threshold voltage, critical dimensions and doping concentration. Both sub-threshold and gate leakage current are considered. A heuristic approach is proposed to determine the vector that causes the maximum leakage power under the influence of random process variations. This vector is then used to estimate the lognormal distribution of the total leakage current of the circuit by summing up the lognormal leakage current distributions of the individual standard cells at their respective input levels. The proposed method has been effective in accurately estimating the leakage mean, standard deviation and probability density function (PDF) of ISCAS-85 benchmark circuits. The average errors of our method compared with near exhaustive random vector testing for mean and standard deviation are 1.32% and 1.41% respectively.

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Statistical timing analysis using bounds and selective enumeration

Cited by 119 publications

References 28 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

A Fully Pipelined Power-Optimization Implementation of Monte Carlo Based SSTA on FPGA

Accurate estimation of vector dependent leakage power in the presence of process variations

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