Statistical timing and leakage power analysis of PD-SOI digital circuits

Abstract

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIM-SOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

“…As technology scales down, leakage current in a sub-micron region becomes more significant and is comparable with the dynamic power dissipation. Figure 1(a) shows the full chip leakage power dissipation based on the international technology roadmap for semiconductor (ITRS) [11] [12]. Various components affecting the subthreshold leakage, gate leakage, and junction leakage are depicted in Figure 1(b).…”