Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC

Valuskar, Ashish; Sudan, Madhu; Rajawat, Arvind

doi:10.1016/j.vlsi.2022.06.009

Cited by 6 publications

(2 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…WiNoCs operate in the sub-THz, mm-wave, THz frequency ranges [21], and zigzag antennas [22] have been identified as the best WiNoC antenna for space-efficient hardware implementation. Amplitude shift keying-on-off keying (ASK-OOK) is widely used in WiNoCs but consumes more energy than quadrature amplitude modulation (QAM) [23]. CMOS-based transceiver modules with OOK designs have been demonstrated with 18 GB/s data throughput at 60 GHz and low size and power overheads [24].…”

Section: Literature Surveymentioning

confidence: 99%

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

Sindgi,

Mahadevaswamy

2024

Bulletin EEI

View full text Add to dashboard Cite

Communication systems at millimeter-wave (mm-wave) frequencies with high propagation losses use radio frequency (RF) budget analysis. RF system gains and losses ensure the receiver can recover the broadcast signal. Modern communication systems use compressive sensing (CS) and discrete wavelet transform (DWT). Hardware implementation is hard. Fieldprogrammable gate arrays (FPGA) adaptability, configurability, and processing speed make them popular. More mm-wave transceivers use FPGAs and advanced signal processing. FPGA-based mm-wave transceivers use compressed sensing and dual-tree complex wavelet transform (DTCWT). RF budget analysis recovers receiver signals. Energy and data efficiency transceivers have baseband processors, transmitters, and receivers. RF-to-mm-wave transmitter. Receiver demodulation and baseband conversion. CS and DTCWT processing modules boost baseband signal processing 5 Gbps Xilinx virtex-6 FPGAs. The system retrieves the signal while conserving power, according to simulations and testing. This study found that FPGA-based mm-wave transceivers can use advanced signal processing in future high-speed communication systems.

show abstract

Section: Literature Surveymentioning

confidence: 99%

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

Sindgi,

Mahadevaswamy

2024

Bulletin EEI

View full text Add to dashboard Cite

show abstract

“…The other limitations with the realistic traffic simulation are the duration of simulation and the requirement of realistic hardware. In [1] the realistic traffic models are simulated for the mixed-torus architecture and the traffic is mainly loaded in the centre of architecture and non uniformly loaded traffics are not analyzed. In the [2] used both the realistic traffic and synthetic traffic patterns to analyze the threat of hardware trojans in the routing process and reduces the average network latency by 38% in realistic traffic and 48% in synthetic traffic patterns.…”

Section: Introductionmentioning

confidence: 99%

Non-Gaussian Traffic Modeling for Multicore Architecture Using Wavelet Based Rosenblatt Process

et al. 2023

View full text Add to dashboard Cite

Networks-on-Chip (NoCs) provides a packet-based communication model for the Systemon-Chip (SoC) architecture to achieve objectives of lower power, higher performance and optimized area. To evaluate NoC performance and explore architectural design options, synthetic traffic models provide better solution in terms of simulation flexibility and faster simulation. In this synthetic traffic, models are generated for the simulation to optimize the computational resources requirements which will be placed inside NoC's architecture before the early design process. In this paper, Wavelet-based Rosenblatt synthetic traffic [RST] is designed and examined which is a non-Gaussian process based on the 2 nd -order Hermite Process. The proposed traffic is applied to SPLASH-2 benchmarks and compared with Gaussian and Non-Gaussian traffic on the parameters of latency, power and buffer-loss. We applied the synthetic traffic on multicore architecture to capture parameters which would be helpful for network designers to choose optimized network resources during the early design architecture. We demonstrate our traffic model: first, how it can be used to describe and acquire non-gaussian burstier traffic on NoC; second, how it can be used to produce synthetic traffic traces that can drive exploration of the early design space for NoCs. Our traffic model helps the chip network designer to choose optimized queue storage inside the router in early design process.

show abstract

Optimum redundancy allocation using spider monkey optimization

et al. 2023

View full text Add to dashboard Cite

Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC

Cited by 6 publications

References 23 publications

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

Non-Gaussian Traffic Modeling for Multicore Architecture Using Wavelet Based Rosenblatt Process

Optimum redundancy allocation using spider monkey optimization

Contact Info

Product

Resources

About