Statistically Aware SRAM Memory Array Design

Grossar, Evelyn; Stucchi, M.; Maex, Karen; Dehaene, Wim

doi:10.1109/isqed.2006.122

Cited by 20 publications

(10 citation statements)

References 20 publications

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“…In order to improve reliability, 6T-cell optimization is a critical step [4], [5]. The cell size determines both the performance and power consumption.…”

Section: Introductionmentioning

confidence: 99%

SNM-aware power reduction and reliability improvement in 45nm SRAMs

Kim

Guthaus

2011

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

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Read stability and write ability are important factors in SRAM design. However, read stability and write ability of the 6T-cell are conflicting design requirements. It is increasingly more difficult to balance these requirements with conventional transistor sizing and V th optimization as technology scales. In this paper, we present a method to help reduce SRAM power consumption by deciding the optimal pull-up transistor size in 6T SRAM cell. Our experiments show that the proposed method can reduce the supply voltage as much as 7-8%. Furthermore, our method has an average 7.76% power reduction in both active and standby mode at 25 • C, a 35% V th variation reduction, 7.78% SNM variation reduction and 11.3% NBTI degradation reduction with at most 1.95% area overhead.

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“…In order to improve reliability, 6T-cell optimization is a critical step [4], [5]. The cell size determines both the performance and power consumption.…”

Section: Introductionmentioning

confidence: 99%

SNM-aware power reduction and reliability improvement in 45nm SRAMs

Kim

Guthaus

2011

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

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“…Unlike memory cells, peripheral circuits use larger, faster and accordingly more leaky transistors in order to satisfy timing requirements. • Memory cells use high threshold voltage transistors which have a significantly lower leakage reduction compared with typical threshold voltage transistors used in peripheral circuit In summary, SRAM memory cells are optimized for low leakage current and area without a significant impact on the cell performance [2,3,8,12,41]. In addition, circuit techniques such as gated-vdd and drowsy cache can be applied to further reduce the memory cell leakage and widen the gap between cell array and peripheral leakage power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Homayoun

Sasan

Gupta

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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Leakage currents in on-chip SRAMs: caches, branch predictor, register files and TLBs, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines, making remaining SRAM components, in particular large drivers, the primary source of leakage. This paper proposes an approach to reduce this source of leakage in all major SRAM-based units of the processor, controlling them in a uniform way, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Four low-power modes are defined, from basic to ultra low power, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to vary from 25% for IL1 to 75% for L2 caches. Resulting temperature reduction, including the effect of positive feedback between temperature and leakage power, is evaluated. A significant temperature reduction is achieved in each unit. It is also shown to reduce hot spots in the instruction TLB and branch predictor.

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“…In summary, SRAM memory cells are optimized for low power (specifically leakage power) and area without a significant impact on the cell performance [13,19,20,21]. In addition, proposed circuit techniques such as gated-Vdd and drowsy cache further reduce the memory cell leakage and only widen the gap between cell array and peripheral leakage power dissipation.…”

mentioning

confidence: 99%

Hot peripheral thermal management to mitigate cache temperature variation

Homayoun

Rahmatian

Kontorinis

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-Modern microprocessor caches are often regarded as cool chip components that dissipate power uniformly. This research demonstrates that this uniformity is a misconception. Memory cell peripherals dissipates considerably higher power than the actual memory cell and this can result in up to 30 o C of temperature difference between the warmest and the coolest cache part. To be effective and accurate, cache temperature and power modeling and management must take this effect into account. We focus on the surrounding logic of the memory cell and apply two novel techniques, peripheral bit swapping (PBS) and peripheral monitor and shutdown (PMSD), to reduce the thermal variation and reduce the corresponding steady-state temperature and leakage power of the cache. Overall, our techniques, on average, decrease temperature by 8 o C for the L1 Data Cache and 5 o C for the shared L2 cache and reduce their thermal gradient by more than 75%, on average, and across SPEC2K benchmarks.I.

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Statistically Aware SRAM Memory Array Design

Cited by 20 publications

References 20 publications

SNM-aware power reduction and reliability improvement in 45nm SRAMs

SNM-aware power reduction and reliability improvement in 45nm SRAMs

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Hot peripheral thermal management to mitigate cache temperature variation

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