Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta&amp;ndash;Sigma Modulators

Pamarti, Sudhakar; Welz, J.; Galton, I.

doi:10.1109/tcsi.2006.887616

Cited by 76 publications

(52 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2) With White Dither: A one-bit pseudorandom dither is added to the LSB of the modulator input [11]. The low-frequency part of the spectrum is degraded due to the noise floor introduced by the dither (see 2): "LSB dither, ").…”

Section: B Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators

Hosseini

Kennedy

2008

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Section: B Simulation Resultsmentioning

confidence: 99%

“…1) to the input [10], [11]. This breaks up the cycles and increases the effective sequence length, resulting in a smoother noise-shaped spectrum.…”

Section: Whenmentioning

confidence: 99%

Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators

Hosseini

Kennedy

2008

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

“…In stochastic approaches, a random signal determines the evolution from one state to the next. These solutions can be analyzed using statistical methods [4]. In deterministic approaches, the DDSM is redesigned so that all trajectories are guaranteed to be longer than a prescribed minimum length.…”

Section: Solving the Problem Of Short Cyclesmentioning

confidence: 99%

Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators

Kennedy

2012

NOLTA

View full text Add to dashboard Cite

Digital Delta-Sigma Modulators (DDSMs) are almost univerally used in integrated circuits for wireless communications and digital audio, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A DDSM is a nonlinear dynamical system which reduces the wordlength of an oversampled digital signal without significantly degrading the SNR in the signal band. DDSMs can exhibit a number of behaviors that are characteristic of nonlinear dynamical systems such as oscillation, coexisting steadystate solutions, sensitivity to initial conditions, and sensitivity to the input. This paper explains the root cause of deterministic spurious and idle tones in DDSMs-short periodic cycles-and describes strategies to eliminate them. The use of a DDSM simplifies the design of analog circuitry in a mixed-signal system. By reducing the bus width in a prescribed way, a DDSM can also permit more efficient downstream digital signal processing-in terms of power and speed-with negligible degradation in performance.

show abstract

“…This property makes the periodicity of the quantization error to depend on the input signal X and the quantization level M = 2 m (where m is the number of bits in the modulator) [3]. One of the most commonly used methods to break the periodicity of a digital RD modulator is to add a pseudo random signal as a least significant bit in the MASH modulator [5,6]. For those previous solutions it was proposed to add the dither signal at the input signal or within the MASH middle stages.…”

Section: Efficient Dither For Digital Mash Rd Modulatorsmentioning

confidence: 99%

Optimized reduction of spur tones in fractional frequency synthesizers

González-Díaz

Garcia-Andrade²,

Espinosa

et al. 2010

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

In this article the contribution of the digital RD modulator in fractional frequency synthesizers is explored. Due to the circuit's non linear behavior, the spur tones generated by the digital RD modulation degrade the synthesizer's phase noise even in regions where the charge pump noise is dominant. A new method to dither digital MASH RD modulators for fractional frequency synthesizers is proposed. The method barely increases the circuit complexity and has the same performance as more cumbersome architectures. Also, a new design consideration to linearize the voltage control oscillator is proposed. Experimental results are obtained in an on-chip fractional synthesizer manufactured in CMOS technology.

show abstract

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators

Cited by 76 publications

References 16 publications

Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators

Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators

Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators

Optimized reduction of spur tones in fractional frequency synthesizers

Contact Info

Product

Resources

About