StatStack: Efficient modeling of LRU caches

Abstract

The identification of the memory gap in terms of the relatively slow memory accesses put a focus on cache performance in the 90s. The introduction of the moderately clocked multicores has shifted this focus from memory latency to memory bandwidth for modern processors. The multicore's limited cache capacity per thread in combination with their current a projected off-chip memory bandwidth limitation makes this the most likely bottleneck of future computer systems.This paper presents a new and efficient way of estimating the cache performance for an application. The method has several similarities with that of Stack Distance, but instead of counting unique memory objects, as is done for Stack Distance calculations, our schema only requires the number of memory accesses to be counted between two successive accesses to the same data object. This task can be efficiently handled at runtime by existing built-in hardware counters. Furthermore, only a small fraction of the memory accesses have to be monitored for an accurate estimation.We show how low-overhead runtime data, similar to that of StatCache, is sufficient to feed this model. We evaluate the accuracy of the proposed transformation based on sparse data and compare the results with that of native stack distance based all memory accesses. We show excellent accuracy over a wide range of cache sizes and applications.

AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance

“…This information is provided as input to the runtime and can be generated with help of a profiling pass. There is a plethora of prior works that use various fast profiling methods to identify which memory instructions miss in the cache hierarchy, such as [1,5,13,23]. Those memory instructions can be targeted for software prefetching as shown by [8,13,23].…”

“…However, in this work we have focused on reuse-distance based methods to model prefetches as they can be targeted to enable improved use of shared resources. Reuse-distance based models such as [1,5] can model miss ratios for individual memory instructions. This information can be used to decide which memory instructions should be targeted for software prefetching.…”

Simulation of Real-time Multiprocessor Scheduling with Overheads

“…These information can be automatically generated or retrieved from a real application. The number of instructions, the memory access rate and the stack distance profile can be generated using tools such as an extension to CacheGrind (Babka et al, 2012), StatStack (Eklov and Hagersten, 2010) or MICA 2 (Hoste and Eeckhout, 2007). The base CPI requires a cycle accurate simulator.…”

Cache Pirating: Measuring the Curse of the Shared Cache

“…MRCs capture an application's cache miss ratio as a function of the cache space available to the applications. MRCs can be generated fairly cheaply [9,6,8], and have been used in contexts such as cache partitioning [14], off-chip bandwidth partitioning [11] and cache contention modeling [7]. However, while MRCs provide significant insight into the miss ratios and data locality of applications, they are limited in their ability to predict performance.…”

“…As long as the the sampling covers all phases of the application fairly, this would allow accurate data collection with a further reduction of the overhead. Such approaches have been used to speed up simulation [16] and stack distance collection [6]. However, we have not implemented this approach.…”