Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

Oprins, Herman; Cherman, Vladimir; Stucchi, M.; Vandevelde, Bart; Plas, G. Van der; Marchal, Paul Alfred; Beyne, Eric

doi:10.1109/stherm.2011.5767190

“…Thermal simulations are used in [4] and [5] to study the thermal effect of various design and technology parameters on 3D ICs subjected to hotspot heat sources. In addition to simulations, studies in [6][7] [8] report also experimental silicon data and expose some important aspects of the heat dissipation behavior in 3D ICs. There is, however, no thorough review of the thermal impact of the TSVbased 3D integration technology.…”

Section: Introductionmentioning

confidence: 99%

Thermal performance of 3D ICs: Analysis and alternatives

Santos

¹

,

Vivet

²

,

Colonna

³

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphitebased heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45ºC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.I.

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“…While different thermal simulators allow to estimate the thermal effects in 3D-chip [1], [11], practical evaluation is more difficult as the typical IR-cam approach has limitation in measuring the different die temperatures [7]. Recently, 3D test chips have been designed to evaluate 3D-integration thermal properties by embedding controllable heaters and thermal sensors [13]. This approach allows to estimate how the heat spreads in the silicon die, but limited only to the available thermal sensors positions.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

Beneventi

¹

,

Bartolini

²

,

Vivet

³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

0

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High temperature is one of the limiting factors and major concerns in 3D-chip integration. In this paper we use a 3D test chip (WIDEIO DRAM on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects. We correlated real temperature measurements with the power dissipated by the heaters using model learning techniques. The resulting compact thermal model is able to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. Results are verified by mean of an off-sample validation technique and show a high accuracy of the compact thermal model when compared with silicon measurements.

show abstract

“…While different thermal simulators allow to estimate the thermal effects in 3D-chip [1], [11], practical evaluation is more difficult as the typical IR-cam approach has limitation in measuring the different die temperatures [7]. Recently, 3D test chips have been designed to evaluate 3D-integration thermal properties by embedding controllable heaters and thermal sensors [13]. This approach allows to estimate how the heat spreads in the silicon die, but limited only to the available thermal sensors positions.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

Beneventi¹,

Bartolini²,

Vivet³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

0

View full text Add to dashboard Cite

High temperature is one of the limiting factors and major concerns in 3D-chip integration. In this paper we use a 3D test chip (WIDEIO DRAM on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects. We correlated real temperature measurements with the power dissipated by the heaters using model learning techniques. The resulting compact thermal model is able to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. Results are verified by mean of an off-sample validation technique and show a high accuracy of the compact thermal model when compared with silicon measurements.

show abstract

Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

Cited by 21 publications

References 17 publications

Thermal performance of 3D ICs: Analysis and alternatives

Thermal performance of 3D ICs: Analysis and alternatives

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

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