Steep coverage-ascent directed test generation for shared-memory verification of multicore chips

Andrade, Gabriel A. G.; Graf, Marleson; Pfeifer, Nicolas; Santos, Luiz C. V. dos

doi:10.1145/3240765.3240852

Cited by 4 publications

(4 citation statements)

References 10 publications

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“…A microarchitecture supporting out-of-order execution was adopted for all cores. For test generation, we adopted a DTG technique [Andrade et al 2018], and employed different test sizes (1ki, 2ki, and 4ki memory operations). For each test size, the generator was executed 12 times exploiting distinct random seeds, leading to 12 test suites containing different programs.…”

Section: Methodology and Main Experimental Resultsmentioning

confidence: 99%

“…The dissertation not only proposed a novel approach as its main scientific contribution [Graf et al 2019], but it also provided innovative technical contributions to test generation leading to high coverage with small effort [Andrade et al 2018, Andrade et al 2020a, Andrade et al 2020b]. Finally, the required implementation effort contributed to the building of a verification framework that is effective to discover errors and can support different architectures and distinct microarchitecture variants.…”

Section: Discussionmentioning

confidence: 99%

“…Since test generators were required to properly evaluate the new checker, the dissertation also involved innovative technical contributions on algorithms for random test generation [Andrade et al 2018] and directed test generation [Andrade et al 2020a, Andrade et al 2020b].…”

Section: Contributionsmentioning

confidence: 99%

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Shared Memory Verification for Multicore Chip Designs

Graf¹,

Santos²

2021

Anais Do XXXIV Concurso De Teses E Dissertações Da SBC (CTD-SBC 2021)

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A multicore chip usually provides a shared memory abstraction implemented by a cache coherence protocol. On-chip coherence can scale gracefully as the number of cores grows, and it plays a major role for general purpose applications. Besides, multicore architectures are likely to relax constraints on store atomicity and on the ordering between loads and stores. As a result, the validation of shared memory faces two main challenges: the higher number of valid execution behaviors and the larger coherence protocol's state space. This dissertation faces those challenges and targets an important design automation phase: the (pre-silicon) functional verification of the shared memory subsystem of a multicore chip, whose behavior is specified by a memory consistency model (MCM). The main scientific contribution is a novel approach to the building of MCM checkers, along with technical contributions on random test generation and directed test generation. The contributions were reported by two papers in a premier IEEE/ACM conference and two articles in the most prestigious IEEE journal on Computer Aided Design of Integrated Circuits and Systems.

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Section: Methodology and Main Experimental Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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Shared Memory Verification for Multicore Chip Designs

Graf¹,

Santos²

2021

Anais Do XXXIV Concurso De Teses E Dissertações Da SBC (CTD-SBC 2021)

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“…In this paper, we focus on debugging the multicore systems which is popular nowadays and propose an automatic debugging tool that leverages the synchronization points to help locating the error-triggered instructions. The current works about multicore systems concentrate on accelerating verification by improving the technique of random test generation [2], [4], [5], [7] and verifying cache coherency [2], [3], [4]. Also, some works are related to the verification of timings [6] and speed debugging the DUT [8].…”

Section: Introductionmentioning

confidence: 99%

An Automatic Debugging Tool of Instruction-Driven Multicore Systems with Synchronization Points

Luo¹,

Yu²

2019

Preprint

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Tracing back the instruction execution sequence to debug a multicore system can be very timeconsuming because the relationships of the instructions can be very complex. For instructions that cannot be checked by the environment immediately after their executions, the errors they triggered can propagate through the instruction execution sequence. Our task is to find the error-triggered instructions automatically. This paper presents an automatic debugging tool that can leverage the synchronization points in the instruction execution sequences of the multicore system being verified to locate the instruction which results in simulation error automatically. To evaluate the performance of the debugging tool, we analyze the complexity of the algorithms and count the number of instructions executed to locate the aimed instruction.

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