Steganography Based Secret Image Sharing Using Block Division Technique

Tulasidasu, M.; Sirisha, B. Lakshmi; Reddy, K. Rasool

doi:10.1109/cicn.2015.227

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…Joshi et al [15] presented the new software-based approach for image hiding and extraction using the 7th bit of pixel replacement by new temporary pixel and also analyze the performance metrics for different images with image quality improvements. Tulsidas et al [16] present a new way of image steganography by using block division method. The block division method generates the maximum pixel value from each block as key and block wise, divide each pixel by maximum value and embedded with cover to generate the stegano image.…”

Section: Related Workmentioning

confidence: 99%

“…The digital watermarking application using image steganography is presented in Chandran et al [20] using different approaches like Discrete Cosine Transform (DCT), DWT, and LSB methods. Most of the recent image steganography articles from [9][10][11][12][13][14][15][16][17][18][19][20] are software-based approaches. Almutairi et al [21] presented the hardware-based steganography using secured LSB method with security, and similarly, the hybrid approach using Haar DWT and Modified LSB method for steganography is made by Simha et al [22] on a hardware platform.…”

Section: Related Workmentioning

confidence: 99%

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Design of an Efficient Steganography Model using Lifting based DWT and Modified-LSB Method on FPGA

Mahesh¹,

K.B²

2019

IJACSA

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The data transmission with information hiding is a challenging task in today world. To protect the secret data or image from attackers, the steganography techniques are essential. The steganography is a process of hiding the information from one channel to another in data communication. In this research work, Design of an Efficient Steganography Model using Lifting Based DWT and Modified-LSB Method on FPGA is proposed. The stegano module includes DWT (Discrete Wavelet Transformation) with lifting scheme for the cover image and encryption with Bit mapping for a secret image, an embedded module using Modified Least Significant Bit (MLSB) Method, and Inverse DWT to generate the stegano image. The recovery module includes DWT, decoding module with pixel extraction and bit retrievals, and decryption to generate the recovered secret image. The steganography model is designed using Verilog-HDL on Xilinx platform and implemented with Artix-7 Field Programmable Gate Array (FPGA). The hardware resource constraints like Area, time, and power utilization of the proposed model results are tabulated. The performance analysis of the work is evaluated using Peak Signal to Noise Ratio (PSNR) and Mean Square Error (MSE) Ratio for a different cover and secret images with better quality. The proposed steganography model operates at high speed, which improves communication performance.

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Section: Related Workmentioning

confidence: 99%