STEPS Towards Cache-Resident Transaction Processing

Abstract

Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately, recent studies show that CPUs are far from realizing their maximum intended throughput because of delays in the processor caches. When running OLTP, instruction-related delays in the memory subsystem account for 25 to 40% of the total execution time. In contrast to data, instruction misses cannot be overlapped with out-of-order execution, and instruction caches cannot grow as the slower access time directly affects the processor speed. The challenge is to alleviate the instructionrelated delays without increasing the cache size.We propose Steps, a technique that minimizes instruction cache misses in OLTP workloads by multiplexing concurrent transactions and exploiting common code paths. One transaction paves the cache with instructions, while close followers enjoy a nearly miss-free execution. Steps yields up to 96.7% reduction in instruction cache misses for each additional concurrent transaction, and at the same time eliminates up to 64% of mispredicted branches by loading a repeating execution pattern into the CPU. This paper (a) describes the design and implementation of Steps, (b) analyzes Steps using microbenchmarks, and (c) shows Steps performance when running TPC-C on top of the Shore storage manager. PrologueIn the past decade, research has proposed techniques to identify and reduce CPU performance bottlenecks in database workloads. As memory access times improve much slower than processor speed, performance is bound by instruction and data cache misses that cause expensive main-memory accesses. Research [AD+99][LB+98] [SBG02] shows that decision-support (DSS) applications are predominantly delayed by data cache misses, whereas OLTP is bounded by instruction cache misses. Although several techniques can reduce data cache misses (larger caches, out-of-order execution, better data placement), none of these can effectively address instruction caches.

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

“…About 88% of instructions, on average, can be fetched together, making a shared fetch mechanism very promising. Previous work also observed a similar phenomenon for server workloads [32] and transaction processing in database systems [33].…”

“…Others have proposed using compiler hints to find reuse [28,29,30,31]. Inter-thread instruction sharing has also been exploited to reduce cache misses [32,33,34]. Our work can be used in conjunction with these intra-thread techniques.…”

Dynamic heterogeneity and the need for multicore virtualization

“…But unlike the reliability examples in Section 5, both of these ideas are alternately very amenable to software support similar to, for example, Cohort Scheduling [20], SEDA [44], and STEPS [16]. All of these alternate projects use additional software complexity to create and exploit dynamic heterogeneity.…”

Cache-Conscious Data Access for DBMS in Multicore Environments

“…Hardavellas et al [9] noticed this problem and pointed out that DB systems must optimize for locality in high-level caches (such as an L1 cache). STEPS [10] improves the L1 instruction-cache performance by scheduling threads in OLTP workloads, but improving the data locality remains a problem for high cache levels. CARIC-DA focuses on the private-cache levels (L1 and L2 caches), which are closer to the processor than the LLC.…”

“…These changes in cache levels indicate that it is increasingly important to bring data beyond the LLC and closer to L1. Hardavellas et al [9] proposed STEPS [10], which is a transactioncoordinating mechanism that minimizes instruction misses in the L1 cache based on the StagedDB design. However, reducing the data misses in higher cache levels is still a major challenge.…”