Stitching a Reference Plane Split Using Routing Layer Traces to Improve I/O Bus Signal Integrity

Abstract

While on-board interconnects are operating at much higher frequencies, the cost of the overall computing system has been decreasing. Computer manufacturers are therefore continuously looking for ways to lower the production cost. In a mobile computing system, where size is a main constraint and expensive high layer count printed circuit board (PCB) technology has been used to control routing congestion, using cheaper technologies with a smaller number of routing layers is an attractive mean of controlling manufacturing cost. On the other hand, routing on a severely size-constrained mobile platform with a smaller number of routing layers can inadvertently expose wide high speed digital interfaces to non-ideal conditions such as reference plane gaps produced by various power and ground islands. Multi-GHz operation of these high speed signals also means that the traditional mitigation method of adding bypass capacitors across the reference gaps is becoming ineffective. In this paper, we propose to use stitching patch underneath the splitting power and ground plane that can be used in conjunction with bypass capacitors to mitigate the effect of these reference plane gaps on signal quality, as well as system EMI and ESD.