Stochastic Matching Properties of FinFETs

Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

“…In addition, to compare the sensitivity of regular and CSRAM cells to a different magnitude of mismatch [17], [18] in the nMOS andpMOS devices, some cells were simulated again. These new simulations included mismatch spreads scaled differently for the two transistor types, proving the different effects on cell yield that mismatches of pMOS and nMOS devices have.…”

“…This means that in addition to a faster operation, CSRAM cells are more suitable for technologies that present a greater mismatch magnitude in the nMOS device than in the pMOS device, as in the case of the FinFETs presented in [17] or some of the devices in [18].…”

Impact of line width roughness on the matching performances of next-generation devices

“…The WL-dependence is noticeably different from the mismatch in planar CMOS: in order to perform a linear regression across the data points, it is necessary to split the experimental σ's into two groups corresponding to devices with (1) the narrowest (W fin = 25 nm, dashed lines) fin width and (2) the larger fins (W fin ≥ 50 nm, plain lines). The improvement in both V T (2.3 and 1.8 mV/μm for n-and p-type FinFETs) and β (1.7 and 0.9% μm for n-and pFinFETs, respectively) mismatch in large devices has been attributed to the undoped nature of the fins and to the corresponding reduction of random dopant fluctuations [21]. On the other hand, it is believed that the degradation of the matching parameters for 25-nm fin widths is linked to enhanced sidewall roughness effects in the narrowest devices.…”

Interpretation of MOS transistor mismatch signature through statistical device simulations

“…Recently, series resistance fluctuations have been studied in case of advanced device architectures such as FinFET, where the access resistance of the source and drain terminals heavily impacted the mismatch behavior [54,55]. A similar effect can be observed in bulk MOS or, actually, in any other active device, when the whole deviceinterconnection system is affected by external (to the device) resistance fluctuations.…”

“…Above threshold, however, the increase of the fluctuations is affected by series resistance fluctuations [54]. The currents delivered by these 1300-µm wide test devices are of the order of milliamperes even at low drain bias ( figure 4.2).…”