Strain compensation by relieving defects in SiGe channel for FinFET technologies

Abstract

Current generations of FinFET devices are incorporating SiGe alloys as stressor material in channel regions in order to enhance hole mobility, drive current and channel conductivity. However, the presence of SiGe gives rise to new issues to be controlled during the device fabrication process, such as the strain retention or defectivity control, as they may seriously impact the quality of the strained SiGe channel and so the final device performance. The present work addresses the study of defect formation during the optimized integration of SiGe FinFETs for 10 nm technology nodes, aimed at determining the Ge threshold content for the nucleation of defects. Due to the relevance of atomistic models in determining the mechanisms and nature of defect formation, molecular dynamics (MD) simulations have been performed to emulate the FinFET fabrication process. The channel region is generated by removing a portion of the total volume of the Si substrate, further refilled with Si 1 − x Ge x alloy to form the co-integrated FinFETs. After deposition, the presence of Ge induces a lattice distortion which is expected to be relieved by defect formation. Samples are annealed varying the Ge fraction, allowing to determine that threshold Ge content for the nucleation of defects is x = 0.27. MD provides also the nature of the formed defects, which have been suggested to be twinning developed at {111} planes and 60• misfit dislocations. Simulation results have been compared to experimental observations, both in good agreement.