Strain Engineering for 3.5-nm Node in Stacked-Nanoplate FET

Kim, Hyunsuk; Son, Dae‐Ho; Myeong, Ilho; Ryu, Donghyun; Park, Jaeyeol; Kang, Myounggon; Jeon, Jongwook; Shin, Hyungcheol

doi:10.1109/ted.2019.2917503

Cited by 12 publications

(6 citation statements)

References 17 publications

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“…4. We benchmark the structure of the NS FETs from previous works [5]- [8]. For a realistic simulation, we include the QME and SHE.…”

Section: ) 3-nm Node Ns Fet Simulationmentioning

confidence: 99%

“…The saturation velocity is assumed to be 2.2×10 7 cm/s [7]. The thermal contact and electrical contact resistance are assumed to be 2×10 -4 cm 2 K/W [8] and 3×10 -9 Ω-cm 2 [7], respectively. A 5×5×2.5 µm 3 Si substrate and an 800-nm back end of lines are included in the simulation for thermal boundaries.…”

Section: ) 3-nm Node Ns Fet Simulationmentioning

confidence: 99%

“…The device is assumed to be surrounded by SiO 2 for isolation. We use the contacted gate pitch (CGP) as an optimization constraint to maintain the device scale in the lateral direction [6]- [8].…”

Section: ) 3-nm Node Ns Fet Simulationmentioning

confidence: 99%

“…As explained in (8), the posterior distribution is assumed to follow normal distribution, N (μ(x),σ 2 (x)). We have depicted posterior mean (μ(x)), with upper/lower bound (μ(x) ± 1.96σ(x)), indicating 95% confidence interval (Fig.…”

Section: A Effective Stopping Condition For the Bo Of Mosfet Devicesmentioning

confidence: 99%

“…Furthermore, the requirements for performance and power consumption have become stricter to meet industrial standards. To minimize SCE multi-gate structures (e.g., finFETs, nanosheet FETs (NS FET)) have been proposed [2]- [8].…”

Section: Introductionmentioning

confidence: 99%

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Bayesian Optimization of MOSFET Devices Using Effective Stopping Condition

Kim

Shin

2021

IEEE Access

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Current nanometer-scale metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit short-channel, quantum, and self-heating effects, making modeling and analysis very complex. A few recent works have employed machine-learning (ML) techniques and neural networks (NN) to model the complex relationships and optimize devices, but a problem with the NN-based device optimization is that it is data-intensive. Bayesian optimization (BO) can realize ML-based data-efficient optimization of the MOSFET device, as it finds the global optimum while requiring few training data. BO stops theoretically when every candidate is explored, so previous works used a fixed number of iterations for the stopping condition. Such an empirical stopping condition is detrimental to the efficiency and reliability of BO, because the global optimum can be found at an earlier stage or even after stopping. Recently, maximum expected improvement (EI max ) with a tiny constant has been proposed as a stopping condition for BO. However, there have not been sufficient works for improving efficiency of BO. By advancing the EI max scheme, we have systemically investigated the effective stopping condition (ESC) for BO of MOSFET devices to boost the efficiency and reliability of optimization. We found that EI max less than a 1% of unit value was an efficient and reliable ESC for optimization, which resulted in upto-87.6% and up-to-47% reductions of required training data compared with the fixed iteration method and the tiny constant method, respectively. Our study provides a novel method to boost efficiency and reliability of BOs for the optimization of MOSFET design in the semiconductor industry.

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“…4. We benchmark the structure of the NS FETs from previous works [5]- [8]. For a realistic simulation, we include the QME and SHE.…”

Section: ) 3-nm Node Ns Fet Simulationmentioning

confidence: 99%

Section: ) 3-nm Node Ns Fet Simulationmentioning

confidence: 99%