Strain Engineering in GeSnSi Materials

Radamson, Henry H.; Noroozi, Mohammad; Jamshidi, Asghar; Thompson, Phillip E.; Östling, Mikael

doi:10.1149/05009.0527ecst

Cited by 29 publications

(22 citation statements)

References 7 publications

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“…The buffer layer can also be a material with a component gradient or gradual component gradient. For GaAs/Si heteroepitaxy, a wide variety of methods using Ge [ 66 ], SiGe [ 19 ], GeSnSi [ 67 ], InGaP [ 68 ] were developed. Among these materials, Ge has been most widely used because of its complete miscibility with Si, well-developed Ge-on-Si growth technology, and nearly the same lattice constant with GaAs [ 69 ].…”

Section: Defect Solution For Iii-v Hetero-epitaxy On (001) Silicon Wafermentioning

confidence: 99%

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Wang

et al. 2022

Nanomaterials

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Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized

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Section: Defect Solution For Iii-v Hetero-epitaxy On (001) Silicon Wafermentioning

confidence: 99%

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Wang

et al. 2022

Nanomaterials

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“…There are several challenges in growing high quality GeSn: (I) the lattice mismatch between Ge and Sn is 14.7% and is even higher at 17% between Sn and Si; (II) incorporation of Sn in Ge is difficult due to the low solubility (<1%) of Sn in Ge and the instability of α-Sn above 13 °C; and (III) Sn precipitation and Sn agglomeration occur during growth. Therefore, growth tools, such as molecular beam epitaxy (MBE) [ 10 , 11 , 12 ], reduced pressure chemical vapor deposition (RPCVD) [ 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 ], ultra vacuum chemical vapor deposition (UHVCVD) [ 23 ], physical vapor deposition (PVD) [ 24 ], and sputtering technique [ 25 , 26 ] have been proposed to grow GeSn at low temperatures. Compared to MBE and PVD, CVD has the advantages of lower costs, higher growth rates, larger wafer sizes, and mass production potential which can easily be transferred to the Si-based microelectronic and photonic industry.…”

Section: Introductionmentioning

confidence: 99%

Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications

et al. 2022

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GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285–320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature.

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“…An effective approach to narrow the bandgap is to apply enhanced tensile lattice strain. Tremendous efforts have been made to enhance tensile strain in Ge, including the introduction of GeSn [ 19 , 20 ], microbridge structures [ 21 , 22 ], external stressors of SiN x [ 23 , 24 ], etc. To date, only a few Ge PD photoelectric detection ranges have been extended due to tensile strain on GOI substrates [ 25 , 26 , 27 , 28 , 29 ], and to the best of our knowledge, there is no report on the performance comparison of p-i-n detectors prepared on GOI with different oxide thickness.…”

Section: Introductionmentioning

confidence: 99%

High Performance p-i-n Photodetectors on Ge-on-Insulator Platform

et al. 2021

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In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 μm, the dark current at −1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at −1 V are as low as 1.79 mA/cm2 and 0.34 μA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip.

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Strain Engineering in GeSnSi Materials

Cited by 29 publications

References 7 publications

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications

High Performance p-i-n Photodetectors on Ge-on-Insulator Platform

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