Strained Si/SiGe n-channel MOSFETs: impact of cross-hatching on device performance

Abstract

The performance of surface channel MOSFET devices depends on the Si/SiO 2 interface quality. The present study has examined the Si/SiO 2 interface of strained Si n-channel MOSFETs fabricated on a Si/SiGe virtual substrate. Evidence of a variation in the oxidation rate of strained Si along the cross-hatch period is presented. The undulating oxide thickness was found to be accompanied by increased nanoscale roughness at the Si/SiO 2 interface for the strained Si surface channel devices compared with conventional MOSFETs. Fluctuations in the strained Si surface channel thickness were additionally caused by the variation in oxidation rate. The control devices exhibited a tighter distribution of electrical characteristics than the strained Si devices due to the non-uniform cross-hatch severity across the Si/SiGe wafer. The results provide strong evidence that significantly enhanced performance of HNMOS surface channel devices is possible through optimization of epitaxial growth methods. Strain in the channel was maintained following device fabrication using a conventional process with a reduced thermal budget.

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

“…The greater dependence of on for the strained Si device may be indicative of slightly higher gate oxide interface roughness than that of the control device. This may arise, for example, from Ge segregation from the SiGe layers into the Si channel leading to nonuniform oxidation rates [12] and consequently gate oxide interface roughness. Interference of Ge during gate oxidation additionally causes de- graded electrical properties of oxides.…”

“…Although it has been shown that a strained layer can be grown on a given alloy composition material to a thickness greater than without relaxation [11], so-called "metastable" material cannot withstand the high thermal budget processing commonly used in MOS fabrication. Consequently, most researchers have attempted fabrication of strained Si/SiGe MOSFETs using reduced thermal budgets and/or by lowering the alloy compositions, ultimately sacrificing the performance gains achievable [12]- [14].…”

SiGe virtual substrate HMOS transistor for analogue applications

“…Although no independent characterisation (i.e. TEM) is available to verify this claim, such defects are known to pose a problem and can be reduced with further optimisation of the epitaxial growth [7]. Nonetheless, combined low-V DS I-V and C-V measurements on long-gate FETs, yielded a drift channel mobility of 20 cm 2 /(V s), at room temperature, indicating that the material quality could, indeed, be an issue.…”

EBIC characterization of strained Si/SiGe heterostructures

“…The misfit and threading dislocations in the strained Si layer can essentially affect the device performance [4][5][6]. An additional factor affecting the device performance is the cross-hatching, a large-scale roughness inherent in such structures due to the stress fields associated with the underlying misfit dislocations generated during relaxation in the graded SiGe layer [7].…”