Strategic Design and Optimization of Vedic Low Pass FIR Filter for ECG Signals

Janwadkar, Sudhanshu; Dhavse, Rasika

doi:10.1007/978-981-16-0275-7_1

Cited by 2 publications

(2 citation statements)

References 19 publications

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“…Janwadkar and Dhavse 11 describe the detailed procedure to finalize the digital LPF specifications in low‐area low‐power constrained scenarios. This work follows the same approach.…”

Section: Filter Implementation and Verification Methodologymentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

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“…Janwadkar and Dhavse 11 describe the detailed procedure to finalize the digital LPF specifications in low‐area low‐power constrained scenarios. This work follows the same approach.…”

Section: Filter Implementation and Verification Methodologymentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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“…Janwadkar and Dhavse 17 designed and optimized a strategic Vedic low‐pass FIR filter for ECG signals denoising. In this paper, the major aim was to reduce the high‐frequency response of ECG signals.…”

Section: Literature Surveymentioning

confidence: 99%

RCVM‐ASS‐CICSKA‐PAPT‐VDF: VLSI design of high‐speed reconfigurable compressed Vedic PAPT‐VDF filter for ECG medical application

Suresh Kumar,

Madhavi

2024

Trans Emerging Tel Tech

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During signal acquisition, the signals are impacted by multiple noise sources that must be filtered before any analysis. However, many different filter implementations in VLSI are dispersed among many studies. This study aims to give readers a systematic approach to designing a Pipelined All‐Pass Transformation based Variable digital filter (PAPT‐VDF) to eliminate the high‐frequency noise from ECG data. The modified design emphasizes first‐ and second‐order responses to obtain high‐speed filter realization with high operating frequencies. The addition of adder and multiplier designs to the hardware architecture of a filter design improves performance. The fundamental blocks of the filter design are the adder and multiplier. The adder and multiplier are employed with an Adaptable stage size‐based concatenation, incremented carry‐skip adder (ASS‐CICSKA), and Improved reconfigurable compressed Vedic multiplier (IRCVM). Utilizing the adder design diminishes the delay with enhanced performance because receiving the carry from an incrementation block is not mandatory. In the multiplier design, the compressor and the reconfigurable approach are adapted with a data detector block to detect the redundant input and lower the logic gates' switching activity with less area overhead. The proposed filter design is implemented in vertex 7 FPGA family device, and the performance measures are analyzed regarding area utilization, delay, power, and frequency. Also, by using the denoised signal, the mean square error (MSE), and signal‐to‐noise ratio (SNR) are evaluated in the MATLAB platform.

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Strategic Design and Optimization of Vedic Low Pass FIR Filter for ECG Signals

Cited by 2 publications

References 19 publications

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

RCVM‐ASS‐CICSKA‐PAPT‐VDF: VLSI design of high‐speed reconfigurable compressed Vedic PAPT‐VDF filter for ECG medical application

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