Strategies for on-chip digital data compression for X-ray pixel detectors

Abstract

The continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of > 1.5× independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of > 4×, > 7×, and > 8× for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12×.

Linking scientific instruments and computation: Patterns, technologies, and experiences

“…Custom silicon may be required for certain data processing steps. 40 , 41 Specialized accelerators may be used for tasks such as ML model training and inference. 42 , 43 , 44 …”

A Hardware Co-design Workflow for Scientific Instruments at the Edge

“…Such synthesis tools incur the cost of higher performance overheads, particularly in resource usage. 4 Leveraging the power of Scala's modern programming language features, Chisel offers higher expressivity, which dramatically improves the productivity and flexibility for constructing synthesizable digital circuits. It also integrates cycleaccurate simulators seamlessly, aiming for lightweight test-driven development, which significantly reduces the barrier to entry for hardware development.…”

“…Since zero (or lower) values dominate the majority of the input data, we employ a bit-shuffling scheme in the encoding stage, which resembles a matrix transpose operation and increases the co-occurrence of zero pixels, to filter out unused higher bits. The bit-shuffling operation can be expressed simply as a set of wires between the input bits and the output bits in the correct order and requires no logic circuit in ASIC; hence it is inexpensive to implement and verify [4]. The output from the encoding stage is variable in size, and multiple encoding blocks generate variable-sized data simultaneously, so no I/O can handle such inputs directly.…”

“…For example, for X-ray pixel detectors, the goal is to develop on-chip data compression algorithms that compress data and can be placed directly adjacent to the internal sensors in the detector ASIC [4]. Since our hardware development resources are currently limited, we focus on co-designing a simple, yet effective, lossless compressor that leverages application-specific characteristics and hardware specialization.…”

High-Performance Ptychographic Reconstruction with Federated Facilities

“…For example, detectors currently used in ptychographic experiments at synchrotron light sources can generate 1030×514 12-bit pixel frames at 3 kHz, yielding a 19.5 Gbps data generation rate. Next-generation light sources, such as the APS upgrade (APSU) [1], are expected to increase X-ray beam brightness by more than two orders of magnitude, an increase that will enable lensless imaging techniques such as ptychography to acquire data at MHz rates [29], potentially increasing data acquisition rates to Tbps. Such dramatically greater data acquisition rates are scientifically exciting but also pose severe technical challenges for data processing systems.…”