Stratix IV FPGA and HardCopy IV ASIC @ 40 nm

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…The Mesh-of-FUs [186] was an exception that targeted both integer and floating-point computation. The architecture was similar to other mesh-based approaches, but the work demonstrated high (at the time) performance capabilities of FPGAs also for floating-point operations, reaching nearly 20 GFLOP/s on a Stratix IV [187] device. Using floating-point processing elements seems to incur a 33% area overhead, yielding a smaller CGRA mesh, and also a (arguably negligible) 13% reduction in clock frequency.…”

From Silicon to Science

“…Thus, compilers are in relatively good shape (though much remains to be done), but research into other key components is extremely rare. The problem of communications with an FPGA (Step 10) has improved dramatically with recent parts that include hard cores for PCIExpress and 8+ Gb/s SERDES [Alfke 2008;Mansur 2008]. Thus, the hardest part of the problem is largely solved; however, these blocks remain difficult to use, because the community still needs to define semantically useful, but generally applicable, interfaces between the support for high speed signaling and the application logic.…”