Stream-Dataflow Acceleration

Abstract

Demand for low-power data processing hardware continues to rise inexorably. Existing programmable and "general purpose" solutions (eg. SIMD, GPGPUs) are insufficient, as evidenced by the order-of-magnitude improvements and industry adoption of application and domain-specific accelerators in important areas like machine learning, computer vision and big data. The stark tradeoffs between efficiency and generality at these two extremes poses a difficult question: how could domain-specific hardware efficiency be achieved without domain-specific hardware solutions? In this work, we rely on the insight that "acceleratable" algorithms have broad common properties: high computational intensity with long phases, simple control patterns and dependences, and simple streaming memory access and reuse patterns. We define a general architecture (a hardware-software interface) which can more efficiently expresses program with these properties called stream-dataflow. The dataflow component of this architecture enables high concurrency, and the stream component enables communication and coordination at very-low power and area overhead. This paper explores the hardware and software implications, describes its detailed microarchitecture, and evaluates an implementation. Compared to a state-of-the-art domain specific accelerator (DianNao), and fixed-function accelerators for MachSuite, Softbrain can match their performance with only 2x power overhead on average.

A Survey of Coarse-Grained Reconfigurable Architecture and Design

“…As a result, a considerable number of CGRAs adopt the other execution models that employ dynamic scheduling or dataflow mechanism to exploit dynamic parallelisms. These models enable high performance for more applications types and alleviate burdens on compilers [19,20,83,84]. The execution models of CGRAs are evolving from static scheduling to dynamic scheduling and from sequential execution to dataflow execution, as indicated in Table 2.…”

“…Polymorphic Pipeline Array supported fine-grained parallelism with software pipeline and coarse-grained pipeline parallelism, which come from ILP and TLP [54]. MLP and DLP support have become a topic in recent CGRAs for data-intensive domains [19,20]. However, there are few CGRAs that support speculative parallelism well, which is an important resource for parallelism exploration.…”

“…Prabhakar et al [19] proposed a CGRA architecture specialized for a parallel patterns programming model in which pattern compute units were specialized for computing nested patterns as a multistage pipeline of SIMD PEs and pattern memory units were specialized for data locality as banked scratch-pad memory and configurable address decoders. Nowatzki et al [20] proposed a so-called stream dataflow architecture that was composed of a CGRA, a control core and a stream memory interface. In this architecture, the design flow begins with a target domain analysis.…”

“…Second, in contrast to one-dimensional spatial computation in the VLIW or superscalar processors, CGRAs advance to two-dimensional spatial computation, which is one of their essential characteristics and is adopted by almost all CGRAs. Third, the dataflow technique is widely used in CGRAs [12,20,62,75]. This technique can be used in hardware to manage the inherent execution order and data preparation order of a static-scheduling DFG, or it can be used to accommodate simultaneous multiple DFGs on a single array.…”

“…The comprehensive comparison provided in Figure 1 compares CGRAs with ASICs, FPGAs, DSPs, GPUs and CPUs in terms of the energy efficiency, flexibility and performance [14,18]. In academia, many researchers consider CGRAs a strong competitor for mainstream computing fabrics, as evidenced by the substantial works published at leading conferences [19,20] and the important foundation supports by, e.g., the Defense Advanced Research Projects Agency (DARPA) [21]. The goal of the DARPA ERI (electronics 118:3 resurgence initiative) is software-defined hardware (SDH) that enables near-ASIC performance (within 10×) without sacrificing programmability for data-intensive algorithms.…”