Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Abstract

Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue the loads/storse necessary to feed their ALU/FPU. Each instruction spent on moving data is a cycle not spent on computation, limiting ALU/FPU utilization to 33% on reductions. We propose "Stream Semantic Registers" to boost utilization and increase energy efficiency. SSR is a lightweight, non-invasive RISC-V ISA extension which implicitly encodes memory accesses as register reads/writes, eliminating a large number of loads/stores. We implement the proposed extension in the RTL of an existing multi-core cluster and synthesize the design for a modern 22nm technology. Our extension provides a significant, 2x to 5x, architectural speedup across different kernels at a small 11% increase in core area. Sequential code runs 3x faster on a single core, and 3x fewer cores are needed in a cluster to achieve the same performance. The utilization increase to almost 100% in leads to a 2x energy efficiency improvement in a multi-core cluster. The extension reduces instruction fetches by up to 3.5x and instruction cache power consumption by up to 5.6x. Compilers can automatically map loop nests to SSRs, making the changes transparent to the programmer.

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

“…In order to store the intermediate data, like the modern processor architectures [15], [18], the ART-9 core also includes a ternary registerfile (TRF) including nine generalpurposed registers, each of which is accessed by using a 2trit value. Utilizing the load-store architecture used for typical RISC processors [19], there are four instruction categories in ART-9 ISA; R-type, I-type, B-type, and M-type.…”

“…As shown in Fig. 4, similar to the lightweight RISC-type designs [19], there are five stages for fetching the instruction from TIM (IF), decoding the fetched instruction (ID), executing the arithmetic/logical operations (EX), accessing the TDM (MEM), and updating the result to TRF (WB). The ternary pipelined registers are newly developed to keep the results from each stage, making a balanced pipelined processing.…”

Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads

“…Aiming to maximize the compute/control ratio (making the FPU the dominant part of the design) mitigating the effects of deep pipelines and dynamic scheduling. 2) An ISA extension, originally proposed by Schuiki et al [18], called stream semantic register (SSR). This extension accelerates data-oblivious [19] problems by providing an efficient semantic to read and write from memory.…”

“…Achieving 3.5× more energy efficiency and 4.5× better FPU utilization on small matrices than the current state of the art. 2) An implementation of the SSR [18] enhanced with shadow registers to allow overlapping loop-setup with ongoing operations using the FREP extension enabling the usage of our SSR and FREP extensions on more irregular kernels such as Fast Fourier Transform (FFT). Achieving speed-ups of 4.7× in the single-core case and close to 3× in the parallel octa-core case for the FFT benchmark.…”

“…The SSR extension was first proposed by Schuiki et al [18], [23]. This hardware extension allows the programmer to configure up to two memory streams with an affine address pattern of dimension N .…”