Stretching the limits of FPGA SerDes for enhanced ATE performance

Abstract

This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test module's functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ~32ps (p-p) jitter, while the loopback path adds ~20ps (p-p) jitter to the input signal.

High speed test interface module using MEMS technology

“…In [11], a test module is designed using standalone mini-testers which consist of a digital logic core (DLC) designed with an FPGA [12][13][14]. This method is suffering from some timing errors duo to XOR multiplexing gates which are known for data dependent jitter (DDJ) in addition to random jitter.…”