Strip warpage analysis of a flip chip package considering the mold compound processing parameters

Chae, MyoungSu; Ouyang, Eric

doi:10.1109/ectc.2013.6575609

Cited by 22 publications

(10 citation statements)

References 10 publications

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“…The flip-chip considered in this study had a process temperature of ≥175 °C. This study was different from other related studies [ 8 , 9 , 10 , 11 , 12 , 13 , 14 ] as the plastic effect of a bump [ 25 ] and the creep effect [ 26 ] were considered in this model. Both effects were input into the simulation model to match a realistic situation.…”

Section: Methodsmentioning

confidence: 93%

“…The CTE measurement results obtained for the substrate agree with the IPC-4101 specification [ 23 ]. Unlike related studies [ 8 , 9 , 10 , 11 , 12 , 13 , 14 ], this study input the temperature variation curves E(T) and α(T) of mold compounds and the substrate into the simulation model, which ensured that the material parameters of the simulation model were close to the actual situation.…”

Section: Methodsmentioning

confidence: 99%

“…For packaging technology, they employed a single-sample window ball grid array, and they obtained simulated values consistent with the trend described by Timoshenko’s bimaterial theory [ 1 ] for the effect of the reflow process on warpage. Chae and Ouyang [ 11 ] discussed the effect of molding temperature on strip warpage for flip-chip strip packaging technology. They discovered that a high molding temperature will cause large strip warpage.…”

Section: Introductionmentioning

confidence: 99%

“…At this point, the strip remains almost flat. As discussed in several papers [ 3 , 9 , 11 , 14 ], strip warpage mainly occurs when the device is cooled to room temperature at 25 °C after the molding process. Severe strip warpage occurring during the post-molding period reduces product yield.…”

Section: Introductionmentioning

confidence: 99%

“…Severe strip warpage occurring during the post-molding period reduces product yield. The literature [ 8 , 9 , 10 , 11 , 12 , 13 , 14 , 20 , 21 , 22 ] indicates that FE simulation is frequently used to solve packaging warpage problems. Material parameters are crucial for determining whether consistency between simulated and experimental values is achieved.…”

Section: Introductionmentioning

confidence: 99%

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Study on the Strip Warpage Issues Encountered in the Flip-Chip Process

Chuang

Chen

2022

Materials

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This study successfully established a strip warpage simulation model of the flip-chip process and investigated the effects of structural design and process (molding, post-mold curing, pretreatment, and ball mounting) on strip warpage. The errors between simulated and experimental values were found to be less than 8%. Taguchi analysis was employed to identify the key factors affecting strip warpage, which were discovered to be die thickness and substrate thickness, followed by mold compound thickness and molding temperature. Although a greater die thickness and mold compound thickness reduce the strip warpage, they also substantially increase the overall strip thickness. To overcome this problem, design criteria are proposed, with the neutral axis of the strip structure located on the bump. The results obtained using the criteria revealed that the strip warpage and overall strip thickness are effectively reduced. In summary, the proposed model can be used to evaluate the effect of structural design and process parameters on strip warpage and can provide strip design guidelines for reducing the amount of strip warpage and meeting the requirements for light, thin, and short chips on the production line. In addition, the proposed guidelines can accelerate the product development cycle and improve product quality with reduced development costs.

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Section: Methodsmentioning

confidence: 93%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Study on the Strip Warpage Issues Encountered in the Flip-Chip Process

Chuang

Chen

2022

Materials

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Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

Park

Kim

et al. 2023

ACS Appl. Mater. Interfaces

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Semiconductor packaging continues to reduce in thickness following the overall thinning of electronic devices such as smartphones and tablets. As the package becomes thinner, the warpage of the semiconductor package becomes more important due to the reduced bending stiffness and driven by thermal residual stresses and thermal expansion mismatch during the epoxy molding compound (EMC) curing to create the package. To address this packaging reliability issue, in this study, we developed a modified cure cycle that adds a rapid cooling step to the conventional cure cycle (CCC) to enhance the reliability of the EMC molded to a copper substrate (EMC/Cu bi-layer package) by lowering the bonding temperature of the EMC/Cu bi-layer package. Modeling of the package via Timoshenko theory including effective cure shrinkage allowed the rapid cooling step to be quantified and confirmed via experiments. The modified cure cycle resulted in a 26% reduction in residual strain, a 27% reduction in curvature, and a 40% increase in peel strength compared to the CCC, suggesting that this is an effective new method for managing warping effects in such packaged structures.

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Bi-directional homogenization equivalent modeling for the prediction of thermo-mechanical properties of a multi-layered printed circuit board (PCB)

Joo

Park

Kim

et al. 2016

J. Micromech. Microeng.

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Warpage of multi-layered printed circuit boards (PCB) during the reflow process is a serious problem which affects the reliability of solder ball connections between the PCB and the mounted semi-conductor packages in electronic devices. It is essential to predict the warpage of the PCB accurately; however, the complicated copper patterns in multi-layered PCBs render a full modeling analysis impossible due to the excessive computing time required. To overcome this problem, we have developed analytical equations of three Cu patterns (line, square, and grid) for the application of thermo-mechanical properties simply by equivalent modeling of Cu patterns. In the proposed equations, the effect of thermo-viscoelastic properties as well as the influence of surrounding layers such as woven glass fabric/BT (bismaleimide triazine), composite laminate (BT core), and photoimageable solder resist (PSR) were considered. To verify the developed equations, vibration tests based on the wave propagation approach were performed at various temperatures. Good agreement was observed between the equivalent model and the experimental results.

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Strip warpage analysis of a flip chip package considering the mold compound processing parameters

Cited by 22 publications

References 10 publications

Study on the Strip Warpage Issues Encountered in the Flip-Chip Process

Study on the Strip Warpage Issues Encountered in the Flip-Chip Process

Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

Bi-directional homogenization equivalent modeling for the prediction of thermo-mechanical properties of a multi-layered printed circuit board (PCB)

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