Strong Crypto for RFID Tags - A Comparison of Low-Power Hardware Implementations

Feldhofer, Martin; Wolkerstorfer, Johannes

doi:10.1109/iscas.2007.378272

Cited by 80 publications

(46 citation statements)

References 5 publications

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“…However, these results come from stand-alone type of design. Although our unified SHA hardware is a little bit larger than the design of [8][9][10], it has an advantage of supporting SHA-1 and SHA-256 hash function on a single data path.…”

Section: Implementation Resultsmentioning

confidence: 99%

Design of Cryptographic Hardware Architecture for Mobile Computing

Kim¹,

Kim²,

Cho³

2009

Journal of Information Processing Systems

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This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

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Section: Implementation Resultsmentioning

confidence: 99%

Design of Cryptographic Hardware Architecture for Mobile Computing

Kim¹,

Kim²,

Cho³

2009

Journal of Information Processing Systems

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“…In particular, we note that the requirements are sufficiently low also for contemporary smart card technologies, because AES-128 and SHA-256 require only about 3,400 and 11,000 gates, respectively [FW07]. As our protocol requires no public-key operations on the token, small smart cards are sufficient.…”

Section: Entitymentioning

confidence: 93%

Embedded SFE: Offloading Server and Network Using Hardware Tokens

Järvinen

Kolesnikov²,

Sadeghi

et al. 2010

Financial Cryptography and Data Security

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Abstract. We consider Secure Function Evaluation (SFE) in the clientserver setting where the server issues a secure token to the client. The token is not trusted by the client and is not a trusted third party. We show how to take advantage of the token to drastically reduce the communication complexity of SFE and computation load of the server. Our main contribution is the detailed consideration of design decisions, optimizations, and trade-offs, associated with the setting and its strict hardware requirements for practical deployment. In particular, we model the token as a computationally weak device with small constant-size memory and limit communication between client and server. We consider semi-honest, covert, and malicious adversaries. We show the feasibility of our protocols based on a FPGA implementation.

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“…To let tags know an ID of a reader, the authors use a symmetric encryption (Feldhofer & Wolkerstorfer, 2007). By decrypting a received message with its own identifier, a tag can know an ID of a reader.…”

Section: Protocol 4 In Pmentioning

confidence: 99%