Structural approach for built-in tests in RF devices

Mannath, Deepa; Webster, D.; Montano-Martinez, Victor; Cohen, David; Kush, Shai; Thiagarajan, Ganesan; Sontakke, Adesh

doi:10.1109/test.2010.5699241

Cited by 23 publications

(13 citation statements)

References 5 publications

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“…Although this approach is highly accurate, it comes at a very high cost, which can amount up to 50% of the overall production cost. Given that RF circuits typically occupy less than 5% of the die area, there is great industrial interest in the reduction of RF test cost [2], [3], [4]. The high cost of RF test is due to the expense of automated test equipment that is required, and, on the other hand, the lengthy test times that result from a sequential measurement approach.…”

Section: ) Recipesmentioning

confidence: 99%

Integrated optimization of semiconductor manufacturing: A machine learning approach

Kupp

Makris

2012

2012 IEEE International Test Conference

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As semiconductor process nodes continue to shrink, the cost and complexity of manufacturing has dramatically risen. This manufacturing process also generates an immense amount of data, from raw silicon to final packaged product. The centralized collection of this data in industry information warehouses presents a promising and heretofore untapped opportunity for integrated analysis. With a machine learningbased methodology, latent correlations in the joint processtest space could be identified, enabling dramatic cost reductions throughout the manufacturing process. To realize such a solution, this work addresses three distinct problems within semiconductor manufacturing: (1) Reduce test cost for analog and RF devices, as testing can account for up to 50% of the overall production cost of an IC; (2) Develop algorithms for post-production performance calibration, enabling higher yields and optimal power-performance; and, (3) Develop algorithms for spatial modeling of sparsely sampled wafer test parameters. Herein these problems are addressed via the introduction of a model-view-controller (MVC) architecture, designed to support the application of machine learning methods to problems in semiconductor manufacturing. Results are demonstrated on a variety of semiconductor manufacturing data from TI and IBM.

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Section: ) Recipesmentioning

confidence: 99%

Integrated optimization of semiconductor manufacturing: A machine learning approach

Kupp

Makris

2012

2012 IEEE International Test Conference

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“…The case study concerns a Bluetooth/Wireless LAN device from Texas Instruments for which a set of ORBiTs [6] are developed to replace the costly standard specification tests. We have at hand measured data from more than one million device instances.…”

Section: Alternativementioning

confidence: 99%

“…The ARM core is used in conjunction with on-die test structures to compute test outcomes; thus, the ORBiTs are entirely internal to the device, and only the test results are reported externally. Further information about the ORBiTs employed can be found in [6].…”

Section: Setting Test Limits On Orbitsmentioning

confidence: 99%

“…Recently, there has been an intensified effort to develop alternative test approaches that relax the requirements on test equipment and/or reduce the associated test times. Among others, the built-in test solution is perhaps the most promising and advantageous [3]- [6]. It relies on extracting on-chip digital, DC or low-frequency test signatures that carry RF information.…”

Section: Introductionmentioning

confidence: 99%

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On proving the efficiency of alternative RF tests

Kupp¹,

Stratigopoulos²,

Drineas³

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The deployment of alternative, low-cost RF test methods in industry has been, to date, rather limited. This is due to the potentially impaired ability to identify device pass/fail labels when departing from traditional specification test. By relying on alternative tests, pass/fail labels must be derived indirectly through new test limits defined for the alternative tests, which may incur error in the form of test escapes or yield loss. Clearly, estimating these test metrics as early as possible in the test development process is key to the success of an alternative test approach. In this work, we employ a test metrics estimation technique based on non-parametric kernel density estimation to obtain such early estimates, and, for the first time, demonstrate a real-world case study of test metric estimation efficiency at parts-per-million levels. To achieve this, we employ a set of more than 1 million RF devices fabricated by Texas Instruments, which have been tested with both traditional specification tests as well as alternative, low-cost On-chip RF Built-in Tests, or "ORBiTs".

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“…Any random defects that affect one or more building blocks within the loop will likely cause fail-to-lock condition. Other methods presented in the literature, such as the structural-based test approach for RF devices in [11] and the defect-oriented test methods for mixed-signal circuits in [12], can effectively detect catastrophic failures at a relatively low cost. We can apply these simple tests first in our test application and terminate the test process once a failure is detected.…”

Section: Test Applicationmentioning

confidence: 99%

Test cost reduction through performance prediction using virtual probe

Chang

Cheng

Zhang

et al. 2011

2011 IEEE International Test Conference

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-The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on their statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with more than 50 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. In this example, the 3σ error of VP prediction is less than 12% for predictable or highly predictable test items. Applying the VP technique can on average replace 59% of test measurement by prediction and, consequently, reduce the overall test time by 57.6%.

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Structural approach for built-in tests in RF devices

Cited by 23 publications

References 5 publications

Integrated optimization of semiconductor manufacturing: A machine learning approach

Integrated optimization of semiconductor manufacturing: A machine learning approach

On proving the efficiency of alternative RF tests

Test cost reduction through performance prediction using virtual probe

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