2012
DOI: 10.1016/j.microrel.2012.05.007
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Structural design guideline to minimize extreme low-k delamination potential in 40nm flip-chip packages

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Cited by 11 publications
(1 citation statement)
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“…4,5 Another reliability issue is delamination of the low-k dialectic layer. 6 Because of the high modulus of copper pillars, which transmits more mechanical stress to the die during the bonding process, and high thermal stress that results from CTE mismatch between the die and substrate, the thermo-mechanical stress causes severe damage to the inherently weak low-k dielectric layer, resulting in delamination of the layer. Because the mechanical properties of porous, low-k materials decrease with lower dielectric constants, 7 this problem will become more severe in the future when materials with a lower dielectric constant are employed.…”
mentioning
confidence: 99%
“…4,5 Another reliability issue is delamination of the low-k dialectic layer. 6 Because of the high modulus of copper pillars, which transmits more mechanical stress to the die during the bonding process, and high thermal stress that results from CTE mismatch between the die and substrate, the thermo-mechanical stress causes severe damage to the inherently weak low-k dielectric layer, resulting in delamination of the layer. Because the mechanical properties of porous, low-k materials decrease with lower dielectric constants, 7 this problem will become more severe in the future when materials with a lower dielectric constant are employed.…”
mentioning
confidence: 99%