2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC) 2009
DOI: 10.1109/vlsisoc.2009.6041334
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Structural heuristics for SAT-based ATPG

Abstract: Abstract-Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. The application of the Boolean satisfiability problem (SAT) to ATPG has been shown to be a robust alternative to traditional ATPG techniques. A major challenge of research in the field of SAT-based ATPG is to obtain a robust algorithm which can solve hard SAT instances reliably without slowing down easy-to-solve SAT instances. This is particular important, since easy-to-solve SAT instances… Show more

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