Structural Optimizations of Silicon Based NMOSFETs with a Sunken STI Pattern by Using a Robust Stress Simulation Methodology

Abstract

As the strained engineering technology of metal-oxide-semiconductor field effect transistors (MOSFET) is scaled beyond the 22 nm node critical dimension, shallow trench isolation (STI) becomes one of the most important resolutions for isolate devices to enhance the carrier mobility of advanced transistors. Several key design factors of n-type MOSFET (NMOSFET) under the resultant loadings of STI structures and contact etching stop layers are sensitively analyzed for silicon channel stress via finite element method-based simulations integrated with the use of design of experienmnts. NMOSFETs with 15 nm deep sunken STI have achieved a ~5% mobility enhancement as compared with a regular STI shape. By adopting simulation-based factorial designs, we have determined that the design factor of recess depth in STI is a critical factor influencing device performance. Moreover, a response surface curve on carrier mobility of NMOSFET under a consideration of combining the sunken STI and source/drain lengths is further presented in this research.