Structural peculiarities and aging effect in hydrogenated a-Si prepared by inductively coupled plasma assisted chemical vapor deposition technique

Nogay, Gizem; Özkol, Engin; İlday, Serim; Turan, Raşit

doi:10.1016/j.vacuum.2014.09.006

Cited by 11 publications

(6 citation statements)

References 55 publications

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“…The peaks of interest in this study are Si*, SiH*, and H α , which are located at 286, 414, and 656 nm, respectively. [ 26 ]…”

Section: Resultsmentioning

confidence: 99%

“…In the photovoltaics (PV) community, optical emission spectroscopy (OES) has been intensively used to identify correlations between layer characteristics and optical emission lines, mostly aiming at detecting the phase transition from amorphous to nanocrystalline silicon growth. [ 22–30 ] Recently, research has been conducted to determine the relation between optical emission spectra and surface passivation for SHJ solar cells. The main research areas can be classified as: quantification of the silane depletion fraction (or crystallization rate index), [ 31–33 ] postdeposition HPT, [ 34,35 ] predeposition treatments (i.e., tuning the background environment of the chamber), [ 36,37 ] and the impact of plasma ignition [ 38 ] on passivation quality.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Silicon Heterojunction Interface Passivation on p‐ and n‐Type Wafers Using Optical Emission Spectroscopy

Özkol

Wagner

Ruske

et al. 2022

Physica Status Solidi (a)

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To increase the efficiency in p‐type wafer‐based silicon heterojunction (SHJ) technology, one of the most crucial challenges is the achievement of excellent surface passivation. Herein, chemical passivation techniques known for n‐type technology are successfully applied on p‐type float–zone (FZ) wafers, and wafer surface passivation quality is correlated with parameters from plasma diagnostics, namely crystallization rate and electron temperature indices. It is shown that plasma ignition at higher powers than deposition powers enhances effective minority carrier lifetimes τeff fourfold for p‐ (0.6–2.1 ms) and sixfold for n‐type (0.6–3.2 ms) wafers while giving opportunity to process under lower electron temperature indices during the nucleation phase. A subsequent hydrogen plasma treatment has a further beneficial effect on chemical passivation, leading to high effective minority carrier lifetimes of 4.5 and 3.1 ms, and implies open‐circuit voltages, i‐VOC, of 735 and 720 mV for p‐ and n‐type wafers, respectively. In particular, cell precursors built on p‐type wafers demonstrate excellent surface passivation with τeff and i‐VOC (4.1 ms and 745 mV). Using these process optimizations, SHJ cells on both p‐ and n‐type wafers are fabricated with efficiencies exceeding 21%.

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“…The peaks of interest in this study are Si*, SiH*, and H α , which are located at 286, 414, and 656 nm, respectively. [ 26 ]…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of Silicon Heterojunction Interface Passivation on p‐ and n‐Type Wafers Using Optical Emission Spectroscopy

Özkol

Wagner

Ruske

et al. 2022

Physica Status Solidi (a)

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show abstract

“…In previous studies, Si films prepared at room temperature via chemical vapor deposition and sputtering exhibit pores and aggregates. 24,25 The dense structures should display intrinsic interfacial phenomena at interfaces with different materials. Furthermore, the thickness of the Si film is controlled at >200 nm without significant changes in the film parameters, indicating that the quality of the film prepared using CAPD is independent of the thickness (See details in SI S6).…”

Section: Structures Of the Si Films Fabricated Via Capdmentioning

confidence: 99%

Formation Processes of a Solid Electrolyte Interphase at a Silicon/Sulfide Electrolyte Interface in a Model All-Solid-State Li-Ion Battery

Asano,

Hata,

Watanabe

et al. 2024

ACS Appl. Mater. Interfaces

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Understanding the electrochemical reactions at the interface between a Si anode and a solid sulfide electrolyte is essential in improving the cycle stabilities of Si anodes in all-solidstate batteries (ASSBs). Highly dense Si films with very low roughnesses of <1 nm were fabricated at room temperature via cathodic arc plasma deposition, which led to the formation of a Si/ sulfide electrolyte model interface. Li (de)alloying through the model interface hardly occurred during the first cycle, whereas it proceeded stably in subsequent cycles. Hard X-ray photoelectron spectroscopy and neutron reflectometry directly revealed that the reduction or oxidation of the interfacial component or Li 3 PS 4 electrolyte occurred during the first cycle. Consequently, an interfacial layer with a thickness of 13 nm and primarily composed of Li 2 S, SiS 2 , and P 2 S 5 glasses was formed during the first cycle. The interfacial layer acted as a Li-conductive, electron-insulating solid electrolyte interphase (SEI) that provided reversible (de)lithiation. Our model interface directly demonstrates the electrochemical reaction processes at the Si/Li 3 PS 4 interface and provides insights into the structures and electrochemical properties of SEIs to activate the (de)lithiation of Si anodes using a sulfide electrolyte.

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“…Many works reported on deposition of silicon dioxide (SiO 2 ), silicon nitride, silicon, and silicon carbide materials for passivation layers, MEMS, and solar cell applications. However, to our knowledge, only a few studies have reported on the use of ICP‐CVD silicon‐based thin films for electronic applications …”

Section: Introductionmentioning

confidence: 99%

Inductively Coupled Plasma Chemical Vapor Deposition for Silicon‐Based Technology Compatible with Low‐Temperature (≤220 °C) Flexible Substrates

Yang

Sagazan

Pichon

et al. 2020

Physica Status Solidi (a)

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Herein, an inductively coupled plasma chemical vapor deposition (CVD) (ICP‐CVD) technique is adopted for deposition of silicon dioxide and silicon thin films to fabricate metal–oxide–semiconductor (MOS) capacitors and thin film transistors (TFTs). Prior to the fabrication and characterization of the TFTs, C–V measurements and breakdown tests are conducted on MOS capacitors based on silicon dioxide deposited under temperatures as low as 20 °C. The breakdown field of 9 MV cm−1 is validated afterward, which implies the good electrical insulating property for acting as a gate insulator and the feasibility of the TFTs. After going through forming gas and thermal annealing with the highest temperature of 220 °C, the TFTs yield good gate insulating properties, a threshold voltage of 3.7 V, an on/off ratio of 6.4 × 102, field effect mobility of 1.2 cm2 (V s)−1, and a subthreshold slope of 3.9 V dec−1. They show promising electrical properties under such a low‐temperature fabrication process using ICP‐CVD technique compatible for silicon electronics using low‐cost flexible substrates.

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Structural peculiarities and aging effect in hydrogenated a-Si prepared by inductively coupled plasma assisted chemical vapor deposition technique

Cited by 11 publications

References 55 publications

Optimization of Silicon Heterojunction Interface Passivation on p‐ and n‐Type Wafers Using Optical Emission Spectroscopy

Optimization of Silicon Heterojunction Interface Passivation on p‐ and n‐Type Wafers Using Optical Emission Spectroscopy

Formation Processes of a Solid Electrolyte Interphase at a Silicon/Sulfide Electrolyte Interface in a Model All-Solid-State Li-Ion Battery

Inductively Coupled Plasma Chemical Vapor Deposition for Silicon‐Based Technology Compatible with Low‐Temperature (≤220 °C) Flexible Substrates

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