STT-MRAM for real-time embedded systems

Abstract

STT-MRAM is an emerging non-volatile memory quickly approaching DRAM in terms of capacity, frequency and device size. Intensified efforts in STT-MRAM research by the memory manufacturers may indicate a revolution with STT-MRAM memory technology is imminent, and therefore it is essential to perform system level research to explore use-cases and identify computing domains that could benefit from this technology. Special STT-MRAM features such as intrinsic radiation hardness, non-volatility, zero stand-by power and capability to function in extreme temperatures makes it particularly suitable for aerospace, avionics and automotive applications. Such applications often have real-time requirementsthat is, certain tasks must complete within a strict deadline. Analyzing whether this deadline is met requires Worst Case Execution Time (WCET) Analysis, which is a fundamental part of evaluating any real-time system. In this study, we investigate the feasibility of using STT-MRAM in real-time embedded systems by analyzing average system performance impact and WCET implications. CCS CONCEPTS • Computer systems organization → Processors and memory architectures; Embedded systems; • Hardware → Non-volatile memory; • Computing methodologies → Real-time simulation;

A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

“…Using SPEC2006 benchmarks on ZSim and DRAMSim2 with timing parameter scaling of 1.2x, 1.5x, and 2.0x, they find an average performance drop of 5.4% and 11.3% in integer and floating-point benchmarks, respectively, when timing parameters are twice that of DRAM. Lastly, considering STT-MRAM's benefits like radiation resistance and zero leakage power, its suitability for real-time systems, including space, automotive, and avionics applications, is evaluated [28]. Using benchmarks tailored for these sectors, the study suggests STT-MRAM could be a strong candidate for this sector.…”

“…Only timing parameters associated with the row buffer differ between DRAM and SOT-MRAM. This is because, following loading a row of data into the buffer, the timing parameters for subsequent operations are identical for both types of memory [28]. The circuitry beyond the row buffer for DRAM and SOT-MRAM is essentially the same [10].…”

“…The cell access mechanism differs between these two memory technologies, leading to differences in the timing parameters related to SOT-MRAM row operations compared to DRAM. The access operation of DRAM is voltage-based, whereas SOT-MRAM's access operation is current-based [28].…”

“…The timing parameter related to precharging a bit line to a reference voltage before the cell access is Row pre-charge (tRP) [10]. In DRAM, to access a cell, a bit line is first pre-charged, and then the word line is activated, enabling the sensing circuit to sense the data.SOT-MRAM cell array access is different from DRAM, as it uses a current operation mode to read data stored in MTJ by activating a word line and applying a small amount of current to sense the data through the bit-line [28].tRCD is the timing parameter that represents the time required to access and retrieve the data from a row and has it ready in the row buffer.tRCD,tRP, and row to row activation delay(tRRD) are three values which differ between DRAM and SOT-MRAM.…”

Tunneling magnetoresistance materials and devices for neuromorphic computing

“…SOT-MRAM, on the other hand, has better endurance and faster switching speed. Based on these pros and cons, STT-MRAM may be more suitable as main memory [110], while SOT-MRAM may be more suitable as L1-L2 cache [111]. However, MRAM still faces some challenges that need to be overcome before it can be practically applied, such as lower on/off rates compared to other RAM and susceptibility to external magnetic fields when used for storage.…”