Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

Abstract

High pressure annealing technique at 6 atm over a wide range of temperature (200-450˚C) was introduced as post metal annealing on high-k/metal gate metal-oxide-semiconductor capacitor. To verify the ability of HPA in improving interface trap density, leakage issue the other MOS capacitor with same structure was annealed by MWA for comparison. The electrical performance of the capacitors under different etching mechanism was analyzed and the difference in characteristics such as flat-band voltage shift, oxide trapped charge, interface state density and leakage current were compared. The results show that high pressure annealing process is more effective to minimize the oxide trapped charged at low temperature than by high power MWA at 3000W, and the reduction in leakage current density after high pressure anneal at low temperature corresponds to the reduction in charge traps. High pressure annealing demonstrates great potential as the post-metallization annealing process for the high-k/metal gate structure .

Study on dopant activation and EOT impact in HKMG stacks using microwave annealing with different frequencies

“…9) Nevertheless, a primary concern with high-k/metal gate (HKMG) electrodes is their thermal instability, which can lead to band gap shifts, increased equivalent oxide thickness (EOT), uncontrollable threshold voltage, and leakage current. [10][11][12][13] The growth of many monolayers of Si-O or Si-N containing materials at the channel interface is considered desirable for improving the high-k/Si interface quality because these layers could provide the essential, high-quality nature of the SiO 2 /Si interface. To boost the high-k/Si interface efficiency, the proper annealing conditions are essential.…”