Studies on Through-Chip Via Filling for Wafer-Level 3D Packaging

Barkey, Dale P.; Callahan, John J.; Keigler, Arthur; Liu, Zhen; Ruff, Al; Trezza, J. A.; Wu, Bang-Hao

doi:10.1149/ma2006-02/35/1642

Meet. Abstr.

2006

DOI: 10.1149/ma2006-02/35/1642

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Studies on Through-Chip Via Filling for Wafer-Level 3D Packaging

Dale P. Barkey

John J. Callahan

Arthur Keigler³

et al.

Abstract: not Available.

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2009

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3D device integration

Bauer¹,

Neuhaus²

2009

2009 11th Electronics Packaging Technology Conference

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For more than a decade the industry has recognized the power of the third dimension in package and sub-system assembly for the implementation of highly integrated mobile electronic products. Numerous approaches have been reported and demonstrated including those base on package stacking (package-on-package, origami, and edge stacked modules) and those based on die stacking (wire bond, mixed technology, edge redistribution, and through-silicon-vias).Through-silicon-vias stand out from the others as the only true 3D device integration as opposed to 3D packaging method. Consequently, through silicon via technology presents unique opportunities and challenges. For example, through-silicon-vias promise unrivaled performance improvements due to short, low impedance interconnect and high silicon efficiency. On the other hand, no other 3D approach matches the disruption of the existing food chain.This paper reviews the challenges and opportunities of 3D device integration based on through-silicon-vias in terms of, processes, applications, challenges, and intellectual property landscape.

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3D device integration

Bauer¹,

Neuhaus²

2009

2009 11th Electronics Packaging Technology Conference

View full text Add to dashboard Cite

show abstract

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Studies on Through-Chip Via Filling for Wafer-Level 3D Packaging

Abstract: not Available.

Cited by 1 publication

References 2 publications

3D device integration

3D device integration

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