Study and Analysis of Retention Time and Refresh Frequency in 1T1C DRAM at Nanometer Regime

Sankpal, Amol S.; Pethe, D. J.

doi:10.1007/978-981-16-3767-4_44

Cited by 1 publication

(1 citation statement)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The performance of a 1T1C DRAM cell is affected due to various leakage sources in the MOS transistor [7]. Leakage is a crucial issue in DRAM, which will bring about the probability of data loss from storage capacitor increase and deteriorate the retention time [15]. Furthermore, optimizing the circuit of the sense amplifier (SA) is an efficient and convenient method to reduce the overall energy consumption of DRAM during some particular operations [16,17].…”

Section: Introductionmentioning

confidence: 99%

Low-Power Single Bitline Load Sense Amplifier for DRAM

Dai,

Lu,

et al. 2023

Electronics

View full text Add to dashboard Cite

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.

show abstract